ADC3244IRGZT Multi-Mode Cellular Base Stations

3 Description
The ADC324x are a high-linearity, ultra-low power,
dual-channel, 14-bit, 25-MSPS to 125-MSPS, analogto-digital converter (ADC) family. The devices are
designed specifically to support demanding, high
input frequency signals with large dynamic range
requirements. An input clock divider allows more
flexibility for system clock architecture design and the
SYSREF input enables complete system
synchronization. The ADC324x family supports serial
low-voltage differential signaling (LVDS) in order to
reduce the number of interface lines, thus allowing for
high system integration density. The serial LVDS
interface is two-wire, where each ADC data are
serialized and output over two LVDS pairs. An
internal phase-locked loop (PLL) multiplies the
incoming ADC sampling clock to derive the bit clock
that is used to serialize the 14-bit output data from
each channel. In addition to the serial data streams,
the frame and bit clocks are also transmitted as
LVDS outputs.