74HC595D 74HCT595 are high-speed Si-gate CMOS devices

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Introduction: Shift Shift Register 1 Element 8 Bit 16-SOIC

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Overview

Model	74HC595D
Pack	SOIC-16

Brand	NXP
Dc	/

Detailed description

The 74HC595; 74HCT595 are high-speed Si-g

ate CMOS devices and are pin compatible

with Low-power Schottky TTL (LSTTL). They

are specified in co

mpliance with JEDEC

standard No. 7A.

The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and

3-state outputs. The regist

ers have separate clocks.

Data is shifted on the positive-going transiti

ons of the shift register clock input (SHCP).

The data in each register is transferred to the storage register on a positive-going

transition of the storage register clock input

(STCP). If both clocks are connected together,

the shift register will always be one cloc

k pulse ahead of th

e storage register.

The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.

It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The

storage register has 8 parallel 3-state bus driv

er outputs. Data in the storage register

appears at the output wheneve

r the output enable input (OE

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