5962-01A1701V9A
| Model | 5962-01A1701V9A |
| Description | Tripple Point to Point IEEE 1355 High Speed Controller |
| PDF file | Total 31 pages (File size: 286K) |
| Chip Manufacturer | ATMEL |
Features
•
3 identical bidirectional link channels allowing full duplex communication under
•
•
•
•
•
•
•
•
•
selectable transmit rate from 1.25 up to 200 Mbit/s in each direction
A COmmunication Memory Interface (COMI) provides autonomous accesses to a
communication memory which are controlled by an arbitration unit, allowing two
TSS901E to share one Dual Port Ram without external arbitration
The scalable databus width (8/16/32 bit) allows flexible integration with any CPU type
Little or big endian mode is configurable
AHOst Control Interface (HOCI) gives read/write accesses to the TSS901E
configuration registers and to the DS-link channels for the controlling CPU
Device control via one of the three links allows its use in systems without a local
controller
Link disconnect detection and parity check at token (data and control) level; possible
checksum generation for packet level check
Power saving mode relying on automatic transmit rate reduction
Auser’s manual of the TSS901E (also called SMCS332) is available at:
http://www.omimo.be/companies/dasa_000.htm
Designed on Atmel MG1140E matrix and packaged into MQFPL196
Tripple Point to
Point IEEE 1355
High Speed
Controller
Description and Applications
The TSS901E provides an interface between a Data-Strobe link - according to the
IEEE Std 1355-1995 specification carrying a simple interprocessor communication
protocol - and a data processing node consisting of a CPU and a communication and
data memory.
The TSS901E offers hardware supported execution of the major parts of the interpro-
cessor communication protocol: data transfer between two nodes of a multi-processor
system is performed with minimal host CPU intervention. The TSS901E can execute
simple commands to provide basic features for system control functions; a provision of
fault tolerant features exists as well.
Although the TSS901E initial exploitation is for use in multi-processor systems where
the high speed links standardisation is an important issue and where reliability is a
requirement, it could be used in applications such as heterogeneous systems or mod-
ules without any communication feature like special image compression chips, some
signal processors, application specific programmable logic or mass memory.
The TSS901E may also be used in single board systems where standardised high
speed interfaces are needed and systems containing "non-intelligent" modules such
as A/D-converter or sensor interfaces which can be assembled with the TSS901E
thanks to the "control by link" feature.
TSS901E
Rev. C – 24-Aug-01
1
