5V9352PFGI
| Model | 5V9352PFGI |
| Description | TQFP-32, Tray |
| PDF file | Total 12 pages (File size: 116K) |
| Chip Manufacturer | IDT |
IDT5V9352
3.3V/2.5V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER
INDUSTRIAL TEMPERATURE RANGE
3.3V/2.5V PHASE-LOCK LOOP CLOCK
DRIVER ZERO DELAY BUFFER
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES OCT 28, 2014
IDT5V9352
FEATURES:
• Phase-lock loop clock distribution for high performance clock
tree applications
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the
outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V/2.5V V
CC
• Spread Spectrum Compatible
• Operating frequency up to 200MHz
• Compatible with Motorola MPC9352
• Available in 32-pin TQFP package
• Use replacement part: 87952AYILF
The 5V9352 is a low-skew, low-jitter, phase-lock loop (PLL) clock driver
targeted for high performance clock tree applications. It uses a PLL to
precisely align, in both frequency and phase. The 5V9352 operates at 2.5V
and 3.3V.
DESCRIPTION:
The 5V9352 features three banks of individually configurable outputs.
The banks are configured with five, four, and two outputs. The internal
divide circuitry allows for output frequency ratios of 1:1, 2:1, 3:1, and 3:2:1.
The output frequency relationship is controlled by the f
SEL
frequency
control pins. The f
SEL
pins, as well as other inputs, are LVCMOS/LVTTL
compatible inputs
Unlike many products containing PLLs, the 5V9352 does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the 5V9352 requires a stabilization
time to achieve phase lock of the feedback signal to the reference signal.
This stabilization time is required, following power up and application of a
fixed-frequency, fixed-phase signal at REFCLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for test purposes by setting the
PLL_EN
to high.
The 5V9352 is available in Industrial temperature range (-40°C to
+85°C).
FUNCTIONAL BLOCK DIAGRAM
BANK A
CCLK
1
REFCLK
REF
PLL
FBIN
FB
2
Q
A
3
VCO
0
0
4
0
Q
A
2
2
Q
A
0
1
6
1
Q
A
1
PLL_En
Q
A
4
BANK B
Q
B
0
VCO_
SEL
1
Q
B
1
f
SELA
0
Q
B
2
Q
B
3
f
SELB
BANK C
1
f
SELC
0
Q
C
0
Q
C
1
MR/OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2003
Integrated Device Technology, Inc.
MAY 2013
DSC 5973/19
