7005S20PFB
| Model | 7005S20PFB |
| Description | Application Specific SRAM, 8KX8, 20ns, CMOS, PQFP64 |
| PDF file | Total 20 pages (File size: 172K) |
| Chip Manufacturer | IDT |
HIGH-SPEED
8K x 8 DUAL-PORT
STATIC RAM
Features
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IDT7005S/L
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True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 35/55ns (max.)
– Commercial:15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7005S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7005L
Active: 700mW (typ.)
Standby: 1mW (typ.)
IDT7005 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
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M/S = H for BUSY output flag on Master,
M/S = L for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Devices are capable of withstanding greater than 2001V
electrostatic discharge
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA, quad flatpack, PLCC, and a 64-pin
thin quad flatpack
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
12L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
Address
Decoder
13
(1,2)
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R
(2)
2738 drw 01
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC 2738/16
