70125S35JI8
| Model | 70125S35JI8 |
| Description | Multi-Port SRAM, 2KX9, 35ns, CMOS, PQCC52 |
| PDF file | Total 15 pages (File size: 128K) |
| Chip Manufacturer | IDT |
HIGH-SPEED
2K x 9 DUAL-PORT
STATIC RAM
WITH BUSY & INTERRUPT
Features
✵
◆
◆
IDT70121S/L
IDT70125S/L
◆
High-speed access
– Commercial: 25/35/45/55ns (max.)
– Industrial: 35ns (max.)
Low-power operation
– IDT70121/70125S
Active: 675mW (typ.)
Standby: 5mW (typ.)
– IDT70121/70125L
Active: 675mW (typ.)
Standby: 1mW (typ.)
◆
◆
◆
◆
◆
◆
◆
◆
Fully asychronous operation from either port
MASTER IDT70121 easily expands data bus width to 18 bits or
more using SLAVE IDT70125 chip
On-chip port arbitration logic (IDT70121 only)
BUSY
output flag on Master;
BUSY
input on Slave
INT
flag for port-to-port communication
Battery backup operation—2V data retention
TTL-compatible, signal 5V (±10%) power supply
Available in 52-pin PLCC
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
10L
A
0L
(1,2)
I/O
0R
-I/O
8R
I/O
Control
BUSY
R
Address
Decoder
11
(1,2)
MEMORY
ARRAY
11
Address
Decoder
A
10R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2654 drw 01
(2)
NOTES:
1. 70121 (MASTER):
BUSY
is non-tri-stated push-pull output.
70125 (SLAVE):
BUSY
is input.
2.
INT
is non-tri-stated push-pull output.
APRIL 2006
1
©2006 Integrated Device Technology, Inc.
DSC 2654/10
