B32521-C1334-M189
| Model | B32521-C1334-M189 |
| Description | CAPACITOR, METALLIZED FILM, POLYESTER, 100 V, 0.33 uF, THROUGH HOLE MOUNT, RADIAL LEADED, LEAD FREE |
| PDF file | Total 45 pages (File size: 772K) |
| Chip Manufacturer | EPCOS |
B32520 ... B32529
General purpose (stacked/wound)
Pulse handling capability
"dV/dt" represents the maximum permissible voltage change per unit of time for non-sinusoidal
voltages, expressed in V/µs.
"k
0
" represents the maximum permissible pulse characteristic of the waveform applied to the
capacitor, expressed in V
2
/µs.
Note:
The values of dV/dt and k
0
provided below must not be exceeded in order to avoid damaging the
capacitor.
dV/dt values
Lead spacing 5 mm
7.5 mm
Technology S
S
V
R
V
RMS
V DC V AC dV/dt in V/µs
50
32 200
63
40 250
120
100
63 300
150
250
160 400
200
400
200 600
275
450
200
630
400 800
S = Stacked, W = Wound
k
0
values
Lead spacing 5 mm
7.5 mm
Technology S
S
V
R
V
RMS
V DC V AC k
0
in V
2
/µs
50
32
20000
63
40
30000
15000
100
63
60000
30000
250
160
200000 100000
400
200
500000 220000
450
200
630
400 1000000
S = Stacked, W = Wound
10 mm
S
W
15 mm
S
W
22.5 mm 27.5 mm 37.5 mm
W
W
W
10 mm
S
W
15 mm
S
W
22.5 mm 27.5 mm 37.5 mm
W
W
W
50
75
150
175
320
30
50
100
125
150
5
10
20
3
4
8
10
15
1
3
5
8.5
12
0.8
1
4
6
6300
15000
75000
140000
400000
3800
10000
50000
100000
190000
850
5000
15000
375
800
4000
10000
18000
130
600
2500
8500
15000
100
200
2000
6000
Please read
Important notes
at the end of this document.
Page 23 of 45
