CH7320A-TEF-I-TR
| Model | CH7320A-TEF-I-TR |
| Description | Consumer Circuit, CMOS, PQFP64, 10 X 10 MM, LEAD FREE, MS-026D, LQFP-64 |
| PDF file | Total 16 pages (File size: 133K) |
| Chip Manufacturer | CHRONTEL |
Chrontel
CH7320
CH7320 DVI Transmitter
F
EATURES
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G
ENERAL
D
ESCRIPTION
The CH7320 is a Chrontel flat panel display product targeted
at PC industry. This transmitter accepts a digital RGB
graphics input signal stream from the Intel's Serial Digital
Video Output (SDVO) interface, performs digital
processing on both data and timing and then transmits
DVI signals through a DVI link.
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit the
data. The CH7320 is able to drive a DFP display at a
pixel rate of up to 165MHz, supporting UXGA
(1600x1200) resolution displays.
The CH7320 has two DVI output ports that allow two
DVI monitors to be switched from a single source. Its
connection detection circuitry will automatically route
the DVI data stream to a correct DVI port that a monitor
is attached to.
CH7320 is pin to pin compatible with CH7315
DVI/HDMI transmitter and CH7319 DVI/HDCP
transmitter.
Digital Visual Interface (DVI 1.0) Transmitter up to
165M pixels/second
Supports switched DVI encoding two outputs port A
and B one at the time
DVI low jitter PLL
DVI hot plug detection
◊
High-speed SDVO (1G~2Gbps) AC-coupled serial
differential RGB inputs
Programmable power management
Fully programmable through a serial port
Configuration through Intel
®
Opcodes
◊
Windows XP and Vista support (including MCE and
64-bit variations)
Offered in a 64-pin LQFP package
◊
Intel® Proprietary.
SDVO _ R (+ ,-)
SDVO _ G (+ ,-)
SDVO _ B (+ ,-)
6
Data Latch ,
Serial to Parallel
30
10 bit -8 bit
decoder
H,V, DE
Interrept
Generation
2
SDVO _ INT (+/ -)
HPDET
2
SDVO _ Clk (+ ,-)
2
TLC , TLC *
TDC 0 , TDC 0 *
TDC 1 , TDC 1 *
TDC 2 , TDC 2 *
2
Clock Driver
2
2
DVI PLL
DVI
Encoder
FIFO
8
DVI
Driver
8
2
2
TLC , TLC *
TDC 0, TDC 0 *
TDC 1, TDC 1 *
TDC 2, TDC 2 *
DVI
Serializer
RESET *
Reset & Control
2
2
VSWING
AS
SPC
SPD
Serial Port
Control
SC _ PROM
SD _ PROM
SC _ DDC
SD _ DDC
Figure 1:
Functional Block Diagram
201-0000-092
Rev. 1.7,
1/7/2014
1
