GM71C17400CLJ-6
| Model | GM71C17400CLJ-6 |
| Description | 4,194,304 WORDS x 4 BIT CMOS DYNAMIC RAM |
| PDF file | Total 10 pages (File size: 102K) |
| Chip Manufacturer | HYNIX |
GM71C(S)17400C/CL
4,194,304 WORDS x 4 BIT
CMOS DYNAMIC RAM
Description
The GM71C(S)17400C/CL is the new
generation dynamic RAM organized 4,194,304
words x 4 bit. GM71C(S)17400C/CL has
realized higher density, higher performance and
various functions by utilizing advanced CMOS
process technology. The GM71C(S)17400C/CL
offers Fast Page Mode as a high speed access
mode. Multiplexed address inputs permit the
GM71C(S)17400C/CL to be packaged in a
standard 300 mil 24(26) pin SOJ, and a standard
300 mil 24(26) pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
System oriented features include single power
supply 5.0V+/-10% tolerance, direct interfacing
capability with high performance logic families
such as Schottky TTL.
Features
* 4,194,304 Words x 4 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (5.0V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
t
RAC
t
CAC
t
RC
GM71C(S)17400C/CL-5
GM71C(S)17400C/CL-6
GM71C(S)17400C/CL-7
50
60
70
13
15
18
90
110
130
t
PC
35
40
45
Pin Configuration
24(26) SOJ
V
CC
I/O1
I/O2
WE
RAS
NC
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
26
25
24
23
22
21
* Low Power
Active : 660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
: 0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Battery backup operation (L-version)
* Test function : 16bit parallel test mode
24(26) TSOP II
V
SS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
V
CC
I/O1
I/O2
WE
RAS
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
26
25
24
23
22
21
V
SS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
8
9
10
11
12
13
19
18
17
16
15
14
8
9
10
11
12
13
19
18
17
16
15
14
(Top View)
Rev 0.1 / Apr’01
