I14305P
| Model | I14305P |
| Description | Speech Synthesizer With RCDG, 300s, CMOS, PDIP28, 0.600 INCH, PLASTIC, DIP-28 |
| PDF file | Total 38 pages (File size: 393K) |
| Chip Manufacturer | WINBOND |
ISD4003 SERIES
Microcontroller Interface
A four-wire (SCLK, MOSI, MISO &
SS
) SPI interface is provided for controlling and addressing
functions. The ISD4003 is configured to operate as a peripheral slave device, with a microcontroller-
based SPI bus interface. Read and write operations are controlled through this SPI interface. An
interrupt signal (
INT
) and internal read only Status Register are provided for handshake purposes.
Programming
The ISD4003 series is also ideal for playback-only applications, where single- or multiple-messages
playback is controlled through the SPI port. Once the desired message configuration is created,
duplicates can easily be generated via a programmer.
7.2. S
ERIAL
P
ERIPHERAL
I
NTERFACE
(SPI) D
ESCRIPTION
The ISD4003 series operates via SPI serial interface with the following protocol.
First, the data transfer protocol assumes that the microcontroller’s SPI shift registers are clocked on
the falling edge of the SCLK. However, for the ISD4003, the protocols are as follows:
1. All serial data transfers begin with the falling edge of
SS
pin.
2.
SS
is held LOW during all serial communications and held HIGH between instructions.
3. Data is clocked in on the rising edge of the SCLK signal and clocked out on the falling edge of
the SCLK signal, with LSB first.
4. Playback and record operations are initiated when the device is enabled by asserting the
SS
pin LOW, shifting in an opcode and an address data to the ISD4003 device (refer to the
Opcode Summary in the following page).
5. The opcodes contain <11 address bits> and <5 control bits>.
6. Each operation that ends with an EOM or Overflow will generate an interrupt. The Interrupt
will be cleared the next time a SPI cycle is initiated.
7. As Interrupt data is shifted out of the MISO pin, control and address data are simultaneously
shifted into the MOSI pin. Care should be taken such that the data shifted in is compatible
with current system operation. Because it is possible to read an interrupt data and start a new
operation within the same SPI cycle.
8. An operation begins with the RUN bit set and ends with the RUN bit reset.
9. All operations begin after the rising edge of
SS
.
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Publication Release Date: October 26, 2005
Revision 1.2
