• Inventory
  • Products
  • Technical Information
  • Circuit Diagram
  • Data Sheet
Data Sheet
Home > Data Sheet > I1750SY
I1750SY

I1750SY

Model I1750SY
Description Speech Synthesizer With RCDG, 100s, PDSO28, 0.300 INCH, LEAD FREE, PLASTIC, SOIC-28
PDF file Total 24 pages (File size: 351K)
Chip Manufacturer WINBOND
ISD1700 SERIES
9 ELECTRICAL CHARACTERISTICS
9.1
DC P
ARAMETERS
PARAMETER
Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Record Current
Playback Current
Erase Current
Standby Current
Input Leakage Current
Input Current Low
Preamp Input Impedance
AnaIn Input Impedance
MIC Differential Input
AnaIn Input Voltage
Gain from MIC to SP+/-
Speaker Output Load
AUX Output Load
Speaker Output Power
SYMBOL
V
DD
V
IL
V
IH
V
OL
V
OH
I
DD_Record
I
DD_Playback
I
DD_Erase
I
SB
I
ILPD1
I
ILPD2
R
MIC+,
R
MIC-
R
AnaIn
V
IN1
V
IN2
A
MSP
R
SPK
R
Aux
Pout
MIN
2.4
V
SS
-0.3
0.7xV
DD
V
SS
-0.3
0.7xV
DD
TYP
[1]
MAX
5.5
0.3xV
DD
V
DD
0.3xV
DD
V
DD
UNITS
V
V
V
V
V
mA
mA
mA
µA
µA
µA
kΩ
kΩ
mV
V
dB
kΩ
mW
mW
mW
mW
V
1
1.2
-3.0
0 to -28
1
V
V
mA
dB
%
CONDITIONS
20
20
20
1
-3
7
42
15
6
8
5
670
313
117
49
V
DD
I
OL
= 4.0 mA
[2]
I
OH
= -1.6 mA
[2]
V
DD
= 5.5 V, No load,
Sampling freq = 12 kHz
[3] [4]
10
±1
-10
300
1
40
Speaker Output Voltage
AUX Output Swing
AUX Output DC Level
AUD
Volume Output
Total Harmonic Distortion
V
OUT1
V
OUT2
V
OUT3
I
AUD
A
Vol
THD
Force V
DD
Force V
SS
, others at Vcc
Power-up AGC
When active
Peak-to-Peak
[5]
Peak-to-Peak
V
IN
= 15~300 mV, AGC =
4.7 µF, V
CC
= 2.4V~5.5V
Across both Speaker pins
When active
V
DD
= 5.5 V
1Vp-p,
V
DD
= 4.4 V
1 kHz sine
wave at
V
DD
= 3 V
AnaIn. R
SPK
V
DD
= 2.4 V
= 8
Ω.
R
SPK
= 8Ω (Speaker),
Typical buzzer
Peak-to-Peak
When active
V
DD
=4.5 V, R
EXT
= 390
8 steps of 4dB each
reference to output
15 mV p-p 1 kHz sine
wave, Cmessage
weighted
Notes:
[1]
[2]
[3]
[4]
[5]
Conditions: V
CC
= 4.5V, 8 kHz sampling frequency and T
A
= 25°C, unless otherwise stated.
LED output during Record operation.
V
CCA
, V
CCD
and V
CCP
are connected together. V
SSA
, V
SSP1,
V
SSP2
and V
SSD
are connected together.
REC
,
PLAY
,
FT
,
FWD
,
ERASE
,
VOL
and
RESET
must be at V
CCD
.
Balanced input signal applied between MIC+ and MIC- as shown in the applications example. Single-ended MIC+ or
MIC- input is recommended no more than 150 mV p-p.
- 14 -
Go Upload

* Only PDF files are allowed for upload

* Enter up to 200 characters.