I1P-L67201V-60
| Model | I1P-L67201V-60 |
| Description | FIFO, 512X9, 60ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28 |
| PDF file | Total 16 pages (File size: 147K) |
| Chip Manufacturer | TEMIC |
L 67201/L 67202
Interface
Block Diagram
MATRA MHS
Pin Configuration
(*)SO plastic 28 pin 300 mils
DIL plastic 28 pin 300 mils
DIL ceramic 28 pin 600 mils
32 pin LCC and PLCC
SO/DIL (top view)
INDEX
LCC (top view)
W
NC
V
CC
I
4
I
3
I
8
I
5
(*) On request only
2
GND
NC
R
Q
4
Q
5
Q
3
Q
8
W
I
8
I
3
I
2
I
1
I
0
XI
FF
Q
0
Q
1
Q
2
Q
3
Q
8
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
I
4
I
5
I
6
I
7
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Q
5
Q
4
R
I
2
I
1
I
0
XI
FF
Q
0
Q
1
NC
Q
2
4 3 2
32 31 30
1
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
14 15 16 17 18 19 20
I
6
I
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
Rev. C (10/11/95)
