IBM043611TLAB-7
| Model | IBM043611TLAB-7 |
| Description | Standard SRAM, 32KX36, 3ns, CMOS, PBGA119, BGA-119 |
| PDF file | Total 22 pages (File size: 320K) |
| Chip Manufacturer | IBM |
IBM043611TLAB4M x 1612/10, 3.3VMMDM15DSU-021045122.
Preliminary
Features
• 32K x 36 or 64K x 18 Organizations
• 0.45 Micron CMOS Technology
• Synchronous Pipeline Mode of Operation with
Self-Timed Late Write
• Single Differential HSTL/GTL Clock
• Single +3.3V Power Supply and Ground
• HSTL/GTL Input and Output levels
• Registered Addresses, Write Enables, Synchro-
nous Select, and Data Ins
• Registered Outputs
IBM041811TLAB
IBM043611TLAB
32K x 36 & 64K x 18 SRAM
• Common I/O
• Asynchronous Output Enable and Power Down
Inputs
• Boundary Scan using limited set of JTAG 1149.1
functions
• Byte Write Capability & Global Write Enable
• 7 x 17 Bump Ball Grid Array Package with
SRAM EDEC Standard Pinout and Boundary
SCAN Order
• Programmable Impedance Output Drivers
Description
The IBM043611TLAB and IBM041811TLAB 1Mb
SRAM
S
are Synchronous Pipeline Mode, high-per-
formance CMOS Static Random Access Memories
that are versatile, have wide I/O, and achieve 4ns
cycle times. Dual differential K clocks are used to ini-
tiate the read/write operation, and all internal opera-
tions are self-timed. At the rising edge of the K clock,
all Addresses, Write-Enables, Sync Select, and
Data Ins are registered internally. Data Outs are
updated from output registers off the next rising
edge of the K clock. An internal Write buffer allows
write data to follow one cycle after addresses and
controls. The chip is operated with a single +3.3V
power supply and is compatible with HSTL/GTL I/O
interfaces.
77H9965.T5
10/98
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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