K1S1616B1A-BI70
| Model | K1S1616B1A-BI70 |
| Description | 1Mx16 bit Uni-Transistor Random Access Memory |
| PDF file | Total 10 pages (File size: 182K) |
| Chip Manufacturer | SAMSUNG |
K1S1616B1A
TIMING WAVEFORM OF WRITE CYCLE(3)
(CS
2
Controlled)
t
WC
Address
t
AS(3)
CS
1
t
AW
CS
2
t
BW
UB, LB
t
WP(1)
WE
t
DW
Data in
Data Valid
t
DH
t
CW(2)
t
WR(4)
Preliminary
UtRAM
Data out
High-Z
High-Z
TIMING WAVEFORM OF WRITE CYCLE(4)
(UB, LB Controlled)
t
WC
Address
t
CW(2)
CS
1
t
AW
CS
2
UB, LB
t
BW
t
AS(3)
t
WP(1)
WE
t
DW
Data in
Data Valid
t
DH
t
WR(4)
Data out
NOTES
(WRITE CYCLE)
High-Z
High-Z
1. A wri
t
e occurs during the overlap(t
WP
) of low CS
1
and low WE. A write begins when CS
1
goes low and WE goes low with asserting
UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran-
sition when CS
1
goes high and WE goes high. The t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the CS
1
going low to the end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR
is applied in case a write ends with CS
1
or WE going high.
-9-
Revision 0.0
October 2003
