K1S32161CD-FI700
| Model | K1S32161CD-FI700 |
| Description | Pseudo Static RAM, 2MX16, 70ns, CMOS, PBGA48, 8 X 6 MM, 0.75 MM PITCH, FBGA-48 |
| PDF file | Total 10 pages (File size: 162K) |
| Chip Manufacturer | SAMSUNG |
K1S32161CD
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB or/and LB=V
IL
)
t
RC
Address
t
OH
Data Out
Previous Data Valid
t
AA
Data Valid
UtRAM
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
RC
Address
t
AA
CS
1
t
CO
t
OH
CS
2
t
HZ
t
BA
UB, LB
t
BHZ
t
OE
OE
t
OLZ
t
BLZ
Data out
High-Z
t
OHZ
Data Valid
t
LZ
TIMING WAVEFORM OF PAGE CYCLE(READ ONLY)
A20~A2
Valid
Address
A1~A0
Valid
Address
Valid
Address
Valid
Address
Valid
Address
t
AA
CS
1
t
PC
CS
2
t
CO
OE
t
OE
DQ15~DQ0
(READ CYCLE)
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
3. t
OE
(max) is met only when OE becomes enabled after t
AA
(max).
4. If invalid address signals shorter than min. t
RC
are continuously repeated for over 4us, the device needs a normal read timing(t
RC
) or
needs to sustain standby state for min. t
RC
at least once in every 4us.
t
PA
Data
Valid
Data
Valid
Data
Valid
Data
Valid
t
OHZ
High Z
-7-
Revision 1.0
April 2005
