K3N5U1000E-GC12
| Model | K3N5U1000E-GC12 |
| Description | MASK ROM, 1MX16, 120ns, CMOS, PDSO44, 0.600 INCH, SOP-44 |
| PDF file | Total 3 pages (File size: 52K) |
| Chip Manufacturer | SAMSUNG |
K3N5V(U)1000E-D(G)C
16M-Bit (2Mx8 /1Mx16) CMOS MASK ROM
FEATURES
•
Switchable organization
2,097,152 x 8(byte mode)
1,048,576 x 16(word mode)
•
Fast access time
3.3V Operation : 100ns(Max.)@C
L
=50pF,
120ns(Max.)@C
L
=100pF
3.0V Operation : 120ns(Max.)@C
L
=100pF
•
Supply voltage : single +3.0V/single +3.3V
•
Current consumption
Operating : 40mA(Max.)
Standby : 30µA(Max.)
•
Fully static operation
•
All inputs and outputs TTL compatible
•
Three state outputs
•
Package
-. K3N5V(U)1000E-DC : 42-DIP-600
-. K3N5V(U)1000E-GC : 44-SOP-600
CMOS MASK ROM
GENERAL DESCRIPTION
The K3N5V(U)1000E-D(G)C is a fully static mask programma-
ble ROM fabricated using silicon gate CMOS process technol-
ogy, and is organized either as 2,097,152 x 8 bit(byte mode) or
as 1,048,576x16 bit(word mode) depending on BHE voltage
level.(See mode selection table)
This device operates with 3.0V or 3.3V power supply, and all
inputs and outputs are TTL compatible.
Because of its asynchronous operation, it requires no external
clock assuring extremely easy operation.
It is suitable for use in program memory of microprocessor, and
data memory, character generator.
The K3N5V(U)1000E-DC is packaged in a 42-DIP and the
K3N5V(U)1000E-GC in a 44-SOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
A
19
.
.
.
.
.
.
.
.
A
0
A
-1
X
BUFFERS
AND
DECODER
MEMORY CELL
MATRIX
(1,048,576x16/
2,097,152x8)
A
18
A
17
A
7
A
6
A
5
A
4
A
3
1
2
3
4
5
6
7
8
9
42 A
19
41 A
8
40 A
9
39 A
10
38 A
11
37 A
12
36 A
13
35 A
14
34 A
15
33 A
16
32 BHE
N.C 1
A
18
A
17
A
7
2
3
4
44 N.C
43 A
19
42 A
8
41 A
9
40 A
10
39 A
11
38 A
12
37 A
13
36 A
14
35 A
15
34 A
16
33 BHE
32 V
SS
31 Q
15
/A
-1
30 Q
7
29 Q
14
28 Q
6
27 Q
13
26 Q
5
25 Q
12
24 Q
4
23 V
CC
A
6
5
A
5
6
A
4
A
3
A
2
7
8
9
Y
BUFFERS
AND
DECODER
SENSE AMP.
DATA OUT
BUFFERS
. . .
A
2
A
1
A
0
10
CE 11
V
SS
12
OE 13
Q
0
14
Q
8
15
Q
1
16
A
1
10
DIP
CE
OE
BHE
CONTROL
LOGIC
Q
0
/Q
8
Q
7
/Q
15
Q
9
17
Q
2
18
Q
10
19
Q
3
20
Q
11
21
Pin Name
A
0
- A
19
Q
0
- Q
14
Q
15
/A
-1
BHE
CE
OE
V
CC
V
SS
N.C
Pin Function
Address Inputs
Data Outputs
Output 15(Word mode)/
LSB Address(Byte mode)
Word/Byte selection
Chip Enable
Output Enable
Power
Ground
No Connection
A
0
11
31 V
SS
CE 12
30 Q
15
/A
-1
V
SS
13
29 Q
7
OE 14
28 Q
14
Q
0
15
27 Q
6
Q
8
16
26 Q
13
Q
1
17
25 Q
5
Q
9
18
24 Q
12
Q
2
19
23 Q
4
Q
10
20
22 V
CC
Q
3
21
Q
11
22
SOP
K3N5V(U)1000E-DC
K3N5V(U)1000E-GC
