K4E151611C-TL60
| Model | K4E151611C-TL60 |
| Description | EDO DRAM, 1MX16, 60ns, CMOS, PDSO44, |
| PDF file | Total 35 pages (File size: 554K) |
| Chip Manufacturer | SAMSUNG |
K4E171611C, K4E151611C
K4E171612C, K4E151612C
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of
memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K
Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features
of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-
refresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung′ s advanced CMOS pro-
cess to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer,
personal computer and portable machines.
FEATURES
•
Part Identification
- K4E171611C-J(T)(5V, 4K Ref.)
- K4E151611C-J(T) (5V, 1K Ref.)
- K4E171612C-J(T)(3.3V, 4K Ref.)
- K4E151612C-J(T)(3.3V, 1K Ref.)
•
Active Power Dissipation
Speed
4K
-45
-50
-60
360
324
288
3.3V
1K
540
504
468
4K
550
495
440
Unit : mW
5V
1K
825
770
715
• Extended Data Out Mode operation
(Fast Page Mode with Extended Data Out)
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in plastic SOJ 400mil and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
•
Refresh Cycles
Part
NO.
K4E171611C
K4E171612C
K4E151611C
K4E151612C
V
CC
5V
3.3V
5V
3.3V
1K
16ms
Refresh
cycle
4K
Refresh period
Normal
64ms
128ms
L-ver
RAS
UCAS
LCAS
W
FUNCTIONAL BLOCK DIAGRAM
Control
Clocks
Vcc
Vss
Lower
Data in
Buffer
Sense Amps & I/O
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
VBB Generator
Refresh Timer
Refresh Control
Row Decoder
DQ0
to
DQ7
•
Performance Range
Speed
-45
-50
-60
Refresh Counter
Memory Array
1,048,576 x16
Cells
OE
DQ8
to
DQ15
t
RAC
45ns
50ns
60ns
t
CAC
13ns
15ns
17ns
t
RC
69ns
84ns
104ns
t
HPC
16ns
20ns
25ns
Remark
5V/3.3V
5V/3.3V
5V/3.3V
A0-A11
(A0 - A9)
*1
A0 - A7
(A0 - A9)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note)
*1
: 1K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
