• Inventory
  • Products
  • Technical Information
  • Circuit Diagram
  • Data Sheet
Data Sheet
Home > Data Sheet > K4E661611D-TC50
K4E661611D-TC50

K4E661611D-TC50

Model K4E661611D-TC50
Description 4M x 16bit CMOS Dynamic RAM with Extended Data Out
PDF file Total 36 pages (File size: 885K)
Chip Manufacturer SAMSUNG
K4E661611D, K4E641611D
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-50 or -60) are optional features of this
family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 EDO Mode DRAM
family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4E661611D-TC(5.0V, 8K Ref.)
- K4E641611D-TC(5.0V, 4K Ref.)
• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
Active Power Dissipation
Unit : mW
Speed
-50
-60
8K
495
440
4K
660
605
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) package
• +5.0V±10% power supply
Refresh Cycles
Part
NO.
K4E661611D*
K4E641611D
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
RAS
UCAS
LCAS
W
Control
Clocks
VBB Generator
Vcc
Vss
Lower
Data in
Buffer
Sense Amps & I/O
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
FUNCTIONAL BLOCK DIAGRAM
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
Refresh Timer
Refresh Control
Row Decoder
DQ0
to
DQ7
Performance Range
Speed
-50
-60
Refresh Counter
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Row Address Buffer
Col. Address Buffer
Memory Array
4,194,304 x 16
Cells
OE
Column Decoder
DQ8
to
DQ15
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
Go Upload

* Only PDF files are allowed for upload

* Enter up to 200 characters.