K4E661612B-TC
| Model | K4E661612B-TC |
| Description | 4M x 16bit CMOS Dynamic RAM with Extended Data Out |
| PDF file | Total 36 pages (File size: 887K) |
| Chip Manufacturer | SAMSUNG |
K4E661612B, K4E641612B
CMOS DRAM
4M x 16bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor-
mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated
using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4E661612B-TC/L(3.3V, 8K Ref., TSOP)
- K4E641612B-TC/L(3.3V, 4K Ref., TSOP)
• Extended Data Out Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• Self-refresh capability (L-ver only)
• LVTTL(3.3V) compatible inputs and outputs
Unit : mW
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic TSOP(II) packages
• +3.3V±0.3V power supply
•
Active Power Dissipation
Speed
-45
-50
-60
•
Refresh Cycles
Part
NO.
K4E661612B*
K4E641612B
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
L-ver
128ms
RAS
UCAS
LCAS
W
8K
360
324
288
4K
468
432
396
FUNCTIONAL BLOCK DIAGRAM
Control
Clocks
Vcc
Vss
Lower
Data in
Buffer
Sense Amps & I/O
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
VBB Generator
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
•
Performance Range
Speed
-45
-50
-60
Refresh Timer
Refresh Control
Refresh Counter
Row Decoder
DQ0
to
DQ7
Memory Array
4,194,304 x 16
Cells
OE
DQ8
to
DQ15
t
RAC
50ns
50ns
60ns
t
CAC
12ns
13ns
15ns
t
RC
74ns
84ns
104ns
t
HPC
17ns
20ns
25ns
A0~A12
(A0~A11)*1
A0~A8
(A0~A9)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
