K4F151611C-JC50T
| Model | K4F151611C-JC50T |
| Description | Fast Page DRAM, 1MX16, 50ns, CMOS, PDSO42 |
| PDF file | Total 34 pages (File size: 895K) |
| Chip Manufacturer | SAMSUNG |
K4F171611C, K4F151611C
K4F171612C, K4F151612C
CMOS DRAM
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-50 or -60), power
consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS-
before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This
1Mx16 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
FEATURES
• Part Identification
- K4F171611C-J(T) (5V, 4K Ref.)
- K4F151611C-J(T) (5V, 1K Ref.)
- K4F171612C-J(T) (3.3V, 4K Ref.)
- K4F151612C-J(T) (3.3V, 1K Ref.)
•
Active Power Dissipation
Unit : mW
Speed
4K
-50
-60
324
288
3.3V
1K
504
468
4K
495
440
5V
1K
770
715
• Fast Page Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II)
400mil packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
•
Refresh Cycles
Part
NO.
K4F171611C
K4F171612C
K4F151611C
K4F151612C
V
CC
5V
3.3V
5V
3.3V
1K
16ms
Refresh Refresh period
cycle
Normal
L-ver
4K
64ms
128ms
RAS
UCAS
LCAS
W
FUNCTIONAL BLOCK DIAGRAM
Control
Clocks
Vcc
Vss
Lower
Data in
Buffer
Sense Amps & I/O
Lower
Data out
Buffer
Upper
Data in
Buffer
Upper
Data out
Buffer
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Decoder
DQ0
to
DQ7
•
Perfomance Range
Speed
-50
-60
Memory Array
1,048,576 x16
Cells
OE
t
RAC
50ns
60ns
t
CAC
15ns
15ns
t
RC
90ns
110ns
t
PC
35ns
40ns
Remark
5V/3.3V
5V/3.3V
A0-A11
(A0 - A9)
*1
A0 - A7
(A0 - A9)
*1
Row Address Buffer
Col. Address Buffer
Column Decoder
DQ8
to
DQ15
Note)
*1
: 1K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
