K4F640812E-TL60T
| Model | K4F640812E-TL60T |
| Description | Fast Page DRAM, 8MX8, 60ns, CMOS, PDSO32, |
| PDF file | Total 20 pages (File size: 169K) |
| Chip Manufacturer | SAMSUNG |
K4F660812E,K4F640812E
8M x 8bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
CMOS DRAM
This is a family of 8,388,608 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power) ar e
optional features of this family. All of this family have CAS -before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Fur-
thermore, Self-refresh operation is available in L-version. This 8Mx8 Fast Page Mode DRAM family is fabricated using Samsung
′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Part Identification
- K4F660812E-JC/L(3.3V, 8K Ref., SOJ)
- K4F640812E-JC/L(3.3V, 4K Ref., SOJ)
- K4F660812E-TC/L(3.3V, 8K Ref., TSOP)
- K4F640812E-TC/L(3.3V, 4K Ref., TSOP)
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
•
Active Power Dissipation
Unit : mW
Speed
-45
-50
-60
•
Refresh Cycles
Part
NO.
K4F660812E*
K4F640812E
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
L-ver
128ms
RAS
CAS
W
Control
Clocks
Vcc
Vss
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V
±0.3V
power supply
4K
432
396
360
8K
324
288
252
FUNCTIONAL BLOCK DIAGRAM
VBB Generator
Refresh Control
Refresh Counter
Memory Array
8,388,608 x 8
Cells
Sense Amps & I/O
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS -before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
•
Performance Range
Speed
-45
-50
-60
Refresh Timer
Row Decoder
Data in
Buffer
DQ0
to
DQ7
Data out
Buffer
OE
t
RAC
45ns
50ns
60ns
t
CAC
12ns
13ns
15ns
t
RC
80ns
90ns
110ns
t
PC
31ns
35ns
40ns
A0~A12
(A0~A11)*1
A0~A9
(A0~A10)*1
Row Address Buffer
Col. Address Buffer
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
