L0805M5R49FN
| Model | L0805M5R49FN |
| Description | RESISTOR, THIN FILM, 0.2 W, 1 %, 300 ppm, 5.49 ohm, SURFACE MOUNT, 0805, CHIP, GREEN |
| PDF file | Total 5 pages (File size: 137K) |
| Chip Manufacturer | VISHAY |
L
Vishay Sfernice
SMD Wraparound Ultra Low Value
Thin Film Resistors
SUGGESTED LAND PATTERN
(to IPC-7351A)
G
min.
X
max.
Z
max.
DIMENSIONS (in millimeter)
CHIP SIZE
Z
max.
0603
0705/0805
1206
1505
2010
Note
• Size 2512 under development
2.37
2.76
3.91
4.66
5.93
G
min.
0.35
0.74
1.85
2.44
3.71
X
max.
0.98
1.40
1.73
1.45
2.67
Option: Enlarged Terminations
For stringent and special power dissipation requirements,
the thermal resistance between the resistive layer and
the solder joint can be reduced using enlarged terminations
chip resistors which are soldered on large and thick
copper pads acting as heat sinks (see application note:
“Power Dissipation in High Precision Vishay Sfernice Chip
Resistors and Arrays (P Thin Film, PRA Arrays, CHP Thick
Film)”:
www.vishay.com/doc?53048).
For enlarged terminations: Please consult Vishay Sfernice.
ELECTRICAL SPECIFICATIONS
Resistance range:
Resistance tolerance:
Power dissipation:
Temperature coefficient:
0.1
Ω
to 9.99
Ω
± 1 % to ± 10 %
0.125 mW to 1 W at + 70 °C
Down to 100 ppm/°C
POWER DERATING CURVE
Rated Power (%)
100
80
60
40
20
0
CLIMATIC SPECIFICATIONS
Operating temp. range:
- 55 °C to + 155 °C
MECHANICAL SPECIFICATIONS
Substrate:
Resistive layer:
Coating:
Terminations:
Alumina
NiCr + Ta
2
O
5
Silicone
Solderable
B type:
SnPb over nickel barrier
N type:
SnAg over nickel barrier
G type:
Gold over nickel barrier
0
20
40
60 70
80
100
120
140 155
Ambient Temperature in °C
TOLERANCE AND TCR VS. OHMIC VALUE
VALUE
RANGE
0R1 < 0R25
0R25 < 0R5
0R5 < 9R99
0R1 < 0R5
0R5 < 9R99
TIGHTEST
TOLERANCE
(%)
1
1
1
10
5
BEST TCR
(ppm/°C)
300
200
100
300
200
TERMINATIONS
N or B
N or B
N or B
G
G
www.vishay.com
58
For technical questions, contact:
sfer@vishay.com
Document Number: 53018
Revision: 29-Oct-09
