M1020-12-167.3316LF
| Model | M1020-12-167.3316LF |
| Description | Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| PDF file | Total 10 pages (File size: 440K) |
| Chip Manufacturer | IDT |
General Guidelines for M and R Divider Selection
M1020/21
VCSO B
ASED
C
LOCK
PLL
Product Data Sheet
Input Reference Clocks
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
General guidelines for M/R divider selection (see
following pages for more detail):
•
A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is
19.44MHz
. The LOL pin should
not be used during loop timing mode.
When
LOL
is to be used for system health monitoring,
the phase detector frequency should be
5MHz
or
greater. Low phase detector frequencies make
LOL
overly sensitive, and higher phase detector
frequencies make
LOL
less sensitive.
•
P Divider Look-Up Table (LUT)
The
P_SEL1
and
P_SEL0
pins select the post-PLL divider
values P1 and P0. The output frequency of the SAW
can be divided by
1
or
2,
or the outputs can be TriStated.
The outputs can be placed into the valid state
combinations as listed in Table 5.
P Values
P_SEL1:0
for FOUT0 for FOUT1
M1020-155.5200 or M1021-155.5200
Implementation of single-ended input has been
facilitated by biasing
nDIF_REF0
and
nDEF_REF1
to Vcc/2,
with 50kΩ to Vcc and 50kΩ to ground. The input clock
structure, and how it is used with either
LVCMOS/LVTTL inputs or a DC- coupled LVPECL
clock, is shown in Figure 4.
.
DIF_REF0
50k
Ω
VCC
50k
Ω
X
50k
Ω
MUX
Output Frequency (MHz)
FOUT0
FOUT1
LVCMOS/
LVTTL
0
0
1
1
0
1
0
1
2
2
1
1
2
1
TriState TriState
77.76 77.76
155.52 155.52
77.76 155.52
N/A
N/A
nDIF_REF0
VCC
0
DIF_REF1
LVPECL
127
Ω
VCC
127
Ω
VCC
50k
Ω
1
Table 5: P Divider Look-Up Table (LUT)
82
Ω
50k
Ω
F
UNCTIONAL
D
ESCRIPTION
The M1020/21 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW delay line provides low jitter
signal performance.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in Tables 3 and 4 on pg. 3. These look-up
tables provide flexibility in both the overall frequency
multiplication ratio (total PLL ratio) and phase detector
frequency.
The M1020/21 includes a Loss of Lock (
LOL
) indicator,
which provides status information to system
management software. A Narrow Bandwidth (
NBW
)
control pin is provided as an additional mechanism for
adjusting PLL loop bandwidth without affecting the
phase detector frequency.
Options are available for Hitless Switching (HS) with or
without Phase Build-out (PBO). They provide
SONET/SDH MTIE and TDEV compliance during a
reference clock reselection.
M1020/21 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
nDIF_REF1
REF_SEL
82
Ω
50k
Ω
M1020/21
Figure 4: Input Reference Clocks
Differential LVPECL Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the
127Ω
and
82Ω
resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
the
50Ω
load termination and the VTT bias voltage.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(
DIF_REF0
or
DIF_REF1
). The inverting reference input pin
(
nDIF_REF0
or
nDIF_REF1
) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or
nDEF_REF1)
is left floating (not
connected), the input will self-bias at VCC/2.
4 of 10
●
Revised 28Jul2004
●
tel (508) 852-5400
