M1020-13I167.3316LF
| Model | M1020-13I167.3316LF |
| Description | Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| PDF file | Total 10 pages (File size: 440K) |
| Chip Manufacturer | IDT |
M1020/21
VCSO B
ASED
C
LOCK
PLL
Product Data Sheet
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
13
15
16
17
18
20
21
22
23
24
25
27
28
29
30
31
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
FOUT1
nFOUT1
FOUT0
nFOUT0
P_SEL1
P_SEL0
nDIF_REF1
DIF_REF1
REF_SEL
nDIF_REF0
DIF_REF0
NC
MR_SEL3
MR_SEL2
MR_SEL0
MR_SEL1
LOL
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Output
Output
No internal terminator
No internal terminator
Power supply ground connections.
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 6.
Power supply connection, connect to +
3.3
V.
Clock output 1. Differential LVPECL (CML, LVDS available).
Clock output 0. Differential LVPECL (CML, LVDS available).
, P divider selection. LVCMOS/LVTTL. See Table 5,
Internal pull-down resistor
1
Post-PLL Look-Up Table (LUT), on pg. 4.
Input
Input
Input
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Internal pull-down resistor
1
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
No internal connection.
Internal pull-down resistor
1
M and R divider value selection. LVCMOS/ LVTTL.
See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100kΩ
.
Logic
0
- Wide bandwidth
, R
IN
= 100kΩ
.
Internal nodes. Connection to these pins can cause erratic
device operation.
Table 2: Pin Descriptions
Biased to Vcc/2
2
Biased to Vcc/2
2
Input
Output
32
34, 35, 36
NBW
DNC
Input
Internal pull-UP resistor
1
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-UP resistors, see
on pg. 8.
Note 2: Biased toVcc/2, with 50kΩ to Vcc and 50kΩ to ground. See
on pg. 8.
Note 3: See
in
on pg. 8.
M1020/21 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
2 of 10
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Revised 28Jul2004
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tel (508) 852-5400
