M1021-12I125.0000LF
| Model | M1021-12I125.0000LF |
| Description | Support Circuit, 1-Func, CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| PDF file | Total 10 pages (File size: 440K) |
| Chip Manufacturer | IDT |
PLL Operation
The M1020/21 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector.
The output of the “R” divider is fed into the minus input
of the phase detector. The phase detector compares its
two inputs. The phase detector output, filtered
externally, causes the VCSO to increase or decrease in
speed as needed to phase- and frequency-lock the
VCSO to the reference input.
The value of the M divider directly affects closed loop
bandwidth.
M1020/21
VCSO B
ASED
C
LOCK
PLL
Product Data Sheet
Loss of Lock Indicator (LOL) Output Pin
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives
LOL
to logic
0
. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the
LOL
output goes to logic
1. The
LOL
pin will return back to logic
0
when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
Guidelines for Using LOL
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
-
Fvcso
=
Fin
×
---
R
For the available M divider and R divider look-up table
combinations, Tables 3 and 4 on pg. 3 list the Total PLL
Ratio as well as Fin when using the
M1020-11-155.5200
or
the
M1021-11-155.5200
.
(See “Ordering Information” on pg.
Post-PLL Divider
The M1020/21 also features a post-PLL (P) divider.
By using the P Divider, the device’s output frequency
(Fout) can be the VCSO center frequency (Fvcso) or
1/2 Fvcso, or 0.
The
P_SEL0
and
P_SEL1
pins select the value for the P
divider. (See Table 5 on pg. 4.)
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
M
Fvcso
-
Fout
=
-------------------
=
Fin
×
-----------------
P
R
×
P
M
In a given application, the magnitude of peak-to-peak
jitter at the phase detector will usually increase as the R
divider is increased. If the LOL pin will be used to detect
an unusual clock condition, or a clock fault, the
MR_SEL3:0
pins should be set to provide a phase detector
frequency of
5MHz
or greater. Otherwise, false
LOL
indications may result. A phase detector frequency of
10MHz
or greater is desirable when reference jitter is
over
500ps
, or when the device is used within a noisy
system environment. Refer to Tables 3 and 4 on pg. 3
for phase detector frequency when using the
M1020-11-155.5200
or the
M1021-11-155.5200
.
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the
FOUT
and
nFOUT
pins of the device. A
logic
0
is then present on the clock net. The impedance
of the clock net is then set to 50Ω by the external circuit
resistors. (This is in distinction to a CMOS output in
TriState, in which case the net goes to a high
impedance and the logic value floats.) The 50Ω
impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50Ω generator to validate the integrity of
clock net and the clock load.
Any unused output (single-ended or differential)
should be left unconnected (floating) in system
application. This minimizes output switching current
and therefore minimizes noise modulation of VCSO.
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
M1020/21 Datasheet Rev 1.0
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
●
5 of 10
●
Revised 28Jul2004
●
tel (508) 852-5400
