M1026-13-175.0000
| Model | M1026-13-175.0000 |
| Description | PLL/Frequency Synthesis Circuit |
| PDF file | Total 14 pages (File size: 480K) |
| Chip Manufacturer | IDT |
Preliminary Information
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
G
ENERAL
D
ESCRIPTION
The M1025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1025/26 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
◆
Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆
Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆
LVPECL clock output (CML and LVDS options available)
◆
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆
Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
◆
AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
◆
Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
◆
Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
◆
Pin-selectable feedback and reference divider ratios
◆
Single 3.3V power supply
◆
Small 9 x 9 mm SMT (surface mount) package
F
EATURES
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using
M1025-11-155.5200 or M1026-11-155.5200
Input Reference
Clock (MHz)
(M1025)
(M1026)
PLL Ratio
(Pin Selectable)
(M1025)
(M1026)
Output Clock
(MHz)
(Pin Selectable)
19.44 or 38.88
77.76
155.52
622.08
8 or 4
2
1
0.25
155.52
or
77.76
Table 1: Example I/O Clock Frequency Combinations
S
IMPLIFIED
B
LOCK
D
IAGRAM
M1025/26
NBW
Loop Filter
AUTO
MR_SEL3:0
4
P_SEL1:0
2
LUT
Figure 2: Simplified Block Diagram
M1025/26 Datasheet Rev 0.1
M1025/26 VCSO Based Clock PLL with AutoSwitch
Revised 11Nov2003
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tel (508) 852-5400
