M1034-11-167.3316LF
| Model | M1034-11-167.3316LF |
| Description | PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| PDF file | Total 14 pages (File size: 201K) |
| Chip Manufacturer | IDT |
Integrated
Circuit
Systems, Inc.
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Preliminary Information
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
AUTO
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Input
Power supply ground connections.
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
Power supply connection, connect to +
3.3
V.
Automatic/manual reselection mode for clock input:
Internal pull-down resistor
1
Logic
1
automatic reselection upon clock failure
(non-revertive)
Logic
0
manual selection only (using
REF_SEL
)
Reference Acknowledgement pin for input mux state; outputs
the currently selected reference input pair:
Logic
1
indicates
nDIF_REF1, DIF_REF1
Logic
0
indicates
nDIF_REF0, DIF_REF0
No internal terminator
Clock output pair. Differential LVPECL (CML, LVDS available).
13
15
16
17
18
20
21
22
23
24
25
27
28
29
30
REF_ACK
FOUT
nFOUT
P_SEL1
P_SEL0
nDIF_REF1
DIF_REF1
REF_SEL
nDIF_REF0
DIF_REF0
NC
MR_SEL3
MR_SEL2
MR_SEL0
MR_SEL1
Output
Output
Internal pull-down resistor
1
Post-PLL, P divider selection. LVCMOS/LVTTL. See Table 5, P
Divider Look-Up Table (LUT), on pg. 4.
Input
Input
Input
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Internal pull-down resistor
1
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
Internal pull-down resistor
1
No internal connection
M and R divider value selection. LVCMOS/ LVTTL.
Internal pull-down resistor
1
See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
Loss of Reference indicator. Asserted when there are no clock
edges at the selected input port for 3 clock edges of the PLL
phase detector.
3
Logic
1
indicates loss of reference.
Logic
0
indicates active reference.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100kΩ
.
Logic
0
- Wide bandwidth
, R
IN
= 100kΩ
.
Table 2: Pin Descriptions
Biased to Vcc/2
2
Biased to Vcc/2
2
Input
31
LOR
Output
32
34, 35, 36
NBW
DNC
Input
Internal pull-UP resistor
1
Do Not Connect.
Note 1: For typical values of internal pull-down and pull-UP resistors, see
DC Characteristics
on pg. 11.
Note 2: Biased to Vcc/2, with 50kΩ to Vcc and 50kΩ to ground. See
Differential Inputs Biased to VCC/2
on pg. 11.
Note 3: See
LVCMOS Output
in
DC Characteristics
on pg. 11.
M1033/34 Preliminary Information 0.1
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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Revised 07Apr2005
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