M1034-16I167.3316
| Model | M1034-16I167.3316 |
| Description | PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| PDF file | Total 14 pages (File size: 201K) |
| Chip Manufacturer | IDT |
Integrated
Circuit
Systems, Inc.
External Loop Filter
To provide stable PLL operation, the M1033/34 requires
the use of an external loop filter. This is provided via the
provided filter pins (see Figure 5).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
OP_IN
4
9
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Preliminary Information
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
For guidance on device or loop filter implementa-
tion, contact CMBU (Commercial Business Unit)
Product Applications at (508) 852-5400.
C
LOOP
OP_OUT
8
5
R
POST
nOP_OUT
nVC
6
7
nOP_IN
VC
Figure 5: External Loop Filter
See Table 7, Example External Loop Filter Component
Values, below.
PLL Bandwidth is affected by loop filter component
values, the “M” value, and the “PLL Loop Constants”
listed in AC Characteristics on pg. 12.
The
MR_SEL3:0
settings can be used to actively change
PLL loop bandwidth in a given application. See “M and
R Divider Look-Up Tables (LUT)” on pg. 3.
Example External Loop Filter Component Values
1
for M1033-yz-155.5200 and M1034-yz-155.5200
VCSO Parameters: K
VCO
= 200kHz/V, R
IN
= 100kΩ (pin NBW = 0), VCSO Bandwidth = 700kHz.
Device Configuration
Example External Loop Filter Comp. Values
F
VCSO
MR_SEL3:0 MDiv NBW
R
LOOP
C
LOOP
R
POST
C
POST
(MHz)
Nominal Performance Using These Values
F
REF
(MHz)
PLL Loop
Bandwidth
315
Hz
270
Hz
315
Hz
250
Hz
270
Hz
266
Hz
Damping Passband
Factor Peaking
(dB)
5.4
6.7
5.4
6.0
6.7
6.2
0.068
0.044
0.068
0.05
0.044
0.05
19.44
2
38.88
3
155.52
155.52
155.52
155.52
155.52
155.52
0000
0101
8
8
0
0
0
0
0
0
6.8
kΩ
12
kΩ
6.8
kΩ
22
kΩ
12
kΩ
47
kΩ
10
µF
10
µF
10
µF
4.7
µF
10
µF
2.2
µF
82
kΩ
82k
Ω
82k
Ω
82k
Ω
82k
Ω
82k
Ω
1000
pF
1000
pF
1000
pF
1000
pF
1000
pF
1000
pF
0 0 0 1 16
0 1 1 0 32
1 0 1 0 16
1 0 1 1 64
77.76
4
77.76
5
155.52
4
155.52
6
Table 7: Example External Loop Filter Component Values
Note 1: K
VCO
, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: This row is for the M1033 only.
Note 3: This row is for the M1034 only.
Note 4: Optimal for system clock filtering.
Note 5: Optimal for loop timing mode or where high input jitter tolerance is needed, phase detector frequency is 4.86 MHz.
Note 6: Optimal for loop timing mode or where high input jitter tolerance is needed, phase detector frequency is 2.43 MHz.
M1033/34 Preliminary Information 0.1
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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