M1034-16I168.0400LF
| Model | M1034-16I168.0400LF |
| Description | PLL Based Clock Driver, 1034 Series, 1 True Output(s), 0 Inverted Output(s), CQCC36, 9 X 9 MM, CERAMIC, LCC-36 |
| PDF file | Total 14 pages (File size: 201K) |
| Chip Manufacturer | IDT |
Integrated
Circuit
Systems, Inc.
M1033/34
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Preliminary Information
D
ETAILED
B
LOCK
D
IAGRAM
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
VC
External
Loop Filter
Components
M1033/34
OP_IN
nOP_IN
NBW
MUX
DIF_REF0
nDIF_REF0
Activity
Detector
0
PLL
Phase
Detector
R
IN
R Div
DIF_REF1
nDIF_REF1
Activity
Detector
1
0
1
R
IN
Loop Filter
Amplifier
Phase
Locked
Loop
(PLL)
SAW Delay Line
Phase
Shifter
VCSO
LOR
REF_ACK
Auto
Ref Sel
M Divider
1
P Divider
(1, 2, or TriState)
TriState
FOUT
nFOUT
REF_SEL
AUTO
MR_SEL3:0
P_SEL1:0
4
2
0
M / R Divider
LUT
P Divider
LUT
Figure 3: Detailed Block Diagram
D
IVIDER
S
ELECTION
T
ABLES
M and R Divider Look-Up Tables (LUT)
The
MR_SEL3:0
pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1033 and M1034 are defined in
Tables 3 and 4 respectively.
M1033 M/R Divider LUT
Phase Det.
Total
Fin for
Freq. for
MR_SEL3:0
M Div R Div PLL
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
Tables 3 and 4 provide example Fin and phase
detector frequencies with
155.52MHz
VCSO
devices (M1033-11-155.5200 and
M1034-11-155.5200).
See “Ordering Information” on pg. 14.
M1034 M/R Divider LUT
Phase Det.
Total
Fin for
Freq. for
MR_SEL3:0
M Div R Div PLL
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
8
32
128
512
2
8
32
128
1
4
16
64
1
4
16
1
4
16
64
1
4
16
64
1
4
16
64
4
16
64
8
8
8
8
2
2
2
2
1
1
1
1
N/A
0.25
0.25
0.25
19.44
19.44
19.44
19.44
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
622.08
622.08
622.08
19.44
4.86
1.215
0.30375
77.76
19.44
4.86
1.215
155.52
38.88
9.72
2.43
N/A
155.52
38.88
9.72
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
4
16
64
256
2
8
32
128
1
4
16
64
1
4
16
1
4
16
64
1
4
16
64
1
4
16
64
4
16
64
4
4
4
4
2
2
2
2
1
1
1
1
N/A
0.25
0.25
0.25
38.88
38.88
38.88
38.88
77.76
77.76
77.76
77.76
155.52
155.52
155.52
155.52
N/A
622.08
622.08
622.08
38.88
9.72
2.43
0.6075
77.76
19.44
4.86
1.215
155.52
38.88
9.72
2.43
N/A
155.52
38.88
9.72
Test Mode
1
Test Mode
1
Table 3: M1033 M/R Divider LUT
Table 4: M1034 M/R Divider LUT
Note 1: Factory test mode; do not use.
Note 1: Factory test mode; do not use.
M1033/34 Preliminary Information 0.1
I n t e g r a t e d C i r c u i t S y s t e m s, I n c .
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Revised 07Apr2005
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