M1040-11-156.2500
| Model | M1040-11-156.2500 |
| Description | VCSO BASED CLOCK PLL WITH AUTOSWITCH |
| PDF file | Total 12 pages (File size: 429K) |
| Chip Manufacturer | ICS |
Power-Up Initialization Function (INIT Pin)
The initialization function provides a short-term override
of the narrow bandwidth mode when the device is
powered up in order to facilitate phase locking.
When
INIT
is set to logic
1
, initialization is enabled. With
NBW
set to logic
1
(narrow bandwidth mode), the
initialization function puts the PLL into wide bandwidth
mode until eight consecutive phase detector cycles
occur without a single LOL event. Once the eight valid
PLL locked states have occurred, the PLL bandwidth is
automatically reduced to narrow bandwidth mode.
When
INIT
is logic
0
, the device is forced into wide
bandwidth mode unconditionally.
External Loop Filter
The M1040 requires the use of an external loop filter
components. These are connected to the provided filter
pins (see Figure 5).
M1040
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Preliminary Information
Because of the differential signal path design, the
implementation consists of two identical
complementary RC filters as shown in
R
LOOP
C
LOOP
R
POST
C
POST
C
POST
R
LOOP
OP_IN
C
LOOP
OP_OUT
R
POST
nOP_OUT
nVC
nOP_IN
VC
Figure 5: External Loop Filter
PLL bandwidth is affected by the total “M” (feedback
divider) value, loop filter component values, and other
device parameters. See Table 6, Example External
PLL Simulator Tool Available
For guidance on device or loop filter implementa-
tion, contact CMBU (Commercial Business Unit)
Product Applications at (508) 852-5400.
Example External Loop Filter Component Values
1
for M1040-yz-155.5200
VCSO Parameters: K
VCO
= 200kHz/V, R
IN
= 100kΩ (pin NBW = 0), VCSO Bandwidth = 700kHz.
Device Configuration
Example External Loop Filter Comp. Values
F
VCSO
MR_SEL2:0 MDiv NBW
R
LOOP
C
LOOP
R
POST
C
POST
(MHz)
Nominal Performance Using These Values
(MHz)
F
REF
PLL Loop
Bandwidth
315
Hz
715
Hz
275
Hz
980
Hz
260
Hz
Damping Passband
Factor Peaking
(dB)
5.4
6.2
3.1
6.0
3.0
0.07
0.05
0.20
0.05
0.20
19.44
2
77.76
3
77.76
2
155.52
3
155.52
2
155.52
155.52
155.52
155.52
155.52
000
010
100
101
8
2
1
8
0
0
0
0
0
6.8
kΩ
3.9
kΩ
12
kΩ
2.7
kΩ
5.6
kΩ
10
µF
10
µF
2.2
µF
10
µF
4.7
µF
82
kΩ
33k
Ω
82k
Ω
47k
Ω
82k
Ω
1000
pF
1000
pF
1000
pF
470
pF
1000
pF
0 1 1 16
Table 6: Example External Loop Filter Component Values
Note 1: K
VCO
, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: Optimal for system clock filtering.
Note 3: Optimal for loop timing mode (LOL or Hitless Switching should not be used).
M1040 Datasheet Rev 0.1
●
8 of 12
●
Revised 11Nov2003
●
tel (508) 852-5400
