M1040-12-167.2820
| Model | M1040-12-167.2820 |
| Description | PLL/Frequency Synthesis Circuit |
| PDF file | Total 12 pages (File size: 447K) |
| Chip Manufacturer | IDT |
M1040
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Preliminary Information
P
IN
D
ESCRIPTIONS
Number
1, 2, 3, 10, 14, 26
4
9
5
8
6
7
11, 19, 33
12
13
15
16
17
Name
GND
OP_IN
nOP_IN
nOP_OUT
OP_OUT
nVC
VC
VCC
FOUT1
nFOUT1
FOUT0
nFOUT0
INIT
I/O
Configuration
Description
Ground
Input
Output
Input
Power
Output
Output
Input
No internal terminator
No internal terminator
Internal pull-UP resistor
1
Internal pull-down
1
Biased to Vcc/2
2
Input
Internal pull-down resistor
1
Input
Internal pull-down resistor
1
Biased to Vcc/2
3
Input
Internal pull-down resistor
1
Input
Internal pull-down resistor
1
Power supply ground connections.
External loop filter connections. See Figure 5,
Power supply connection, connect to +
3.3
V.
Clock output pair 1. Differential LVPECL.
Clock output pair 0. Differential LVPECL.
Power-on Initialization; LVCMOS/LVTTL:
Logic
1
allows device to enter narrow mode if
selected (in addition must have 8 LOL=0 counts)
Logic
0
forced device into wide bandwidth mode.
Post-PLL , P divider selection. LVCMOS/LVTTL.
See Table 4, P Divider Selector Values
Reference Differential LVPECL/ LVDS
clock input Differential LVPECL/ LVDS, or single
pair 1.
ended LVCMOS/ LVTTL
Reference clock input selection. LVCMOS/LVTTL.
Logic
1
selects DIF_REF1/nDIF_REF1 inputs
Logic
0
selects DIF_REF0/nDIF_REF0 inputs
Reference Differential LVPECL/ LVDS
clock input Differential LVPECL/ LVDS, or single
pair 0.
ended LVCMOS/ LVTTL
Automatic/manual reselection mode for clock input:
Logic
1
automatic reselection upon clock failure
(non-revertive)
Logic
0
manual selection only (using
REF_SEL
)
M and R divider value selection. LVCMOS/ LVTTL.
See Table 3, M and R Divider Look-Up Tables (LUT)
on pg. 3.
Reference Acknowledgement pin for input mux state;
outputs the currently selected reference input pair:
Logic
1
indicates
nDIF_REF1, DIF_REF1
Logic
0
indicates
nDIF_REF0, DIF_REF0
Loss of Lock indicator output.
4
Logic
1
indicates loss of lock.
Logic
0
indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1
- Narrow loop bandwidth
, R
IN
= 2100kΩ
.
Logic
0
- Wide bandwidth
, R
IN
= 100kΩ
.
Do Not Connect.
Table 2: Pin Descriptions
18
20
21
22
23
24
P_SEL
nDIF_REF1
DIF_REF1
REF_SEL
nDIF_REF0
DIF_REF0
25
27
28
29
30
AUTO
MR_SEL2
MR_SEL1
MR_SEL0
REF_ACK
Input
Internal pull-UP resistor
1
Output
31
LOL
Output
Internal pull-UP resistor
1
32
34, 35, 36
Note 1:
Note 2:
Note 3:
Note 4:
NBW
DNC
Input
For typical values of internal pull-down and pull-up resistors, see
on pg. 10.
Biased to Vcc/2, with 50kΩ to Vcc and 50kΩ to ground. Float if using DIF_REF1 as LVCMOS input. See
on pg. 10.
Biased to Vcc/2, with 50kΩ to Vcc and 50kΩ to ground. Float if using DIF_REF0 as LVCMOS input. See
on pg. 10.
See LVCMOS Outputs in DC Characteristics on pg. 10.
M1040 Datasheet Rev 0.1
●
2 of 12
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Revised 11Nov2003
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tel (508) 852-5400
