M11B16161A-50J
| Model | M11B16161A-50J |
| Description | EDO DRAM, 1MX16, 50ns, CMOS, PDSO42, SOJ-42 |
| PDF file | Total 16 pages (File size: 203K) |
| Chip Manufacturer | ESMT |
$ %
CAPACITANCE
(Ta = 25
°
C , V
CC
= 5V
±
10% or 3.3V
±
10%)
PARAMETER
Input Capacitance (address)
Input Capacitance (
RAS
,
CASH
,
CASL
,
WE
,
OE
)
Output capacitance (I/O0~I/O15)
SYMBOL
C
I1
C
I2
C
I / O
TYP
-
-
-
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
MAX
5
7
10
UNIT
pF
pF
pF
AC ELECTRICAL CHARACTERISTICS
(Ta = 0 to 70
°
C , V
CC
=5V
±
10% or 3.3V
±
10%, V
SS
= 0V) (note 14)
Test Conditions
Input timing reference levels : 0.8V, 2.4V (for 5V power supply), 0.8V, 2.0V (for 3.3V power supply)
Output reference level : V
OL
= 0.8V, V
OH
=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed t
T
= 2ns
PARAMETER
Read or Write Cycle Time
Read Write Cycle Time
EDO-Page-Mode Read or Write Cycle
Time
EDO-Page-Mode Read-Write Cycle
Time
Access Time From
RAS
Access Time From
CAS
Access Time From
OE
Access Time From Column Address
Access Time From
CAS
Precharge
RAS
Pulse Width
RAS
Pulse Width (EDO Page Mode)
RAS
Hold Time
RAS
Precharge Time
CAS
Pulse Width
CAS
Hold Time
CAS
Precharge Time
RAS
to
CAS
Delay Time
CAS
to
RAS
Precharge Time
SYMBOL
t
RC
t
RWC
t
PC
t
PCM
t
RAC
t
CAC
t
OAC
t
AA
t
ACP
t
RAS
t
RASC
t
RSH
t
RP
t
CAS
t
CSH
t
CP
t
RCD
t
CRP
t
ASR
t
RAH
t
RAD
t
ASC
t
CAH
t
AR
t
RAL
t
ACH
-45
MIN
77
97
16
53
45
11
11
22
25
45
45
6
28
6
35
6
10
5
0
6
8
0
6
40
23
10
23
34
10,000
10,000
100,000
50
50
7
30
7
37
7
11
5
0
7
9
0
7
44
25
11
MAX
MIN
84
110
20
58
-50
MAX
MIN
104
135
25
68
50
13
13
25
28
10,000
100,000
60
60
10
40
10,000
10
40
10
37
14
5
0
10
25
12
0
10
55
30
13
-60
MAX
UNIT Notes
ns
ns
ns
ns
22
22
4
5,20
13,20
20
60
15
15
30
33
10,000
100,000
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
10,000
ns
ns
ns
24
19
6,23
7,18
19
45
ns
ns
ns
ns
Row Address Setup Time
Row Address Hold Time
RAS
to Column Address Delay Time
30
ns
ns
ns
ns
ns
ns
8
18
18
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference
to
RAS
)
Column Address to
RAS
Lead Time
Column Address setup to
CAS
precharge
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
4/16
