M11B16161SA-50T
| Model | M11B16161SA-50T |
| Description | EDO DRAM, 1MX16, 50ns, CMOS, PDSO44, TSOP2-50/44 |
| PDF file | Total 16 pages (File size: 203K) |
| Chip Manufacturer | ESMT |
$ %
TRUTH TABLE
FUNCTION
Standby
Read : Word
Read : Lower Byte
Read : Upper Byte
Write : Word (Early Write)
Write : Lower Byte (Early)
RAS
CASL CASH
M11B16161A / M11B16161SA
M11L16161A / M11L16161SA
ADDRESSES
WE
X
H
H
H
L
L
OE
DQ
S
High-Z
Data-Out
Lower Byte, Data-Out
Upper Byte, Data-Out
Data-In
Lower Byte, Data-In ,
Upper Byte, High-Z
Lower Byte, High-Z ,
Upper Byte, Data-In
Data-Out, Data-In
Data-Out
Data-Out
Data-Out
NOTES
ROW
X
ROW
ROW
ROW
ROW
ROW
COL
X
COL
COL
COL
COL
COL
H
L
L
L
L
L
H
Æ
X
L
L
H
L
L
H
Æ
X
L
H
L
L
H
X
L
L
L
X
X
Write : Upper Byte (Early)
Read-Write
1st Cycle
EDO-Page-Mode
2nd Cycle
Read
Any Cycle
EDO-Page-Mode 1st Cycle
Write
2nd Cycle
EDO-Page-Mode 1st Cycle
Read-Write
2nd Cycle
Hidden Refresh
RAS
-Only Refresh
L
L
L
L
L
L
L
L
L
L
Æ
H
Æ
L
L
H
Æ
L
H
L
H
Æ
L
H
Æ
L
L
Æ
H
H
Æ
L
H
Æ
L
H
Æ
L
H
Æ
L
L
H
L
L
L
H
Æ
L
H
Æ
L
L
Æ
H
H
Æ
L
H
Æ
L
H
Æ
L
H
Æ
L
L
H
L
L
X
ROW
ROW
ROW
COL
COL
COL
COL
H
Æ
L L
Æ
H
H
H
H
L
L
L
L
L
X
X
1, 2
2
2
2
1
1
1, 2
1, 2
2
ROW
COL
COL
Data-In
Data-In
Data-Out, Data-In
Data-Out, Data-In
Data-Out
High-Z
H
Æ
L L
Æ
H
H
Æ
L L
Æ
H
H
X
H
L
X
X
ROW
COL
COL
ROW
ROW
X
COL
CBR Refresh
X
High-Z
3
*Note : 1. These WRITE cycles may also be BYTE WRITE cycles (either
CASL
or
CASH
active).
2. These READ cycles may also be BYTE READ cycles (either
CASL
or
CASH
active).
3. Only one
CAS
must be active (
CASL
or
CASH
).
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2001
Revision
:
1.3
7/16
