M11L416256A-40T
| Model | M11L416256A-40T |
| Description | EDO DRAM, 256KX16, 40ns, CMOS, PDSO40, TSOP2-44/40 |
| PDF file | Total 16 pages (File size: 231K) |
| Chip Manufacturer | ESMT |
(OLWH07
(Continued)
PARAMETER
Read Command Hold Time Reference to
CAS
Read Command Hold Time Reference to
RAS
SYMBOL
M11L416256A/M11L416256SA
-25
0
0
3
3
15
6
0
5
22
5
7
5
0
5
22
34
21
17
1.5
50
8
32
10
5
7
4
4
2
2
0
4
3
3
100
43
-50
7
10
5
7
4
4
2
2
0
5
3
3
5
5
-50
7
0
5
24
5
7
5
0
5
24
38
25
19
1.5
50
8
32
10
10
10
4
4
2
2
0
5
3
3
100
55
-50
7
0
0
3
3
15
7
0
5
26
5
8
6
0
5
26
46
31
25
1.5
50
8
32
10
10
10
4
4
2
2
0
5
3
3
100
65
-50
7
-28
0
0
3
3
15
8
0
5
30
5
9
7
0
5
30
51
34
26
2.5
50
8
32
10
10
10
5
5
2
2
0
6
3
3
100
75
-50
7
-30
0
0
3
3
15
8
0
5
34
5
10
8
0
5
34
56
36
27
2.5
50
8
32
-35
0
0
3
3
15
8
-40
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
9,15,19
9
20
10,17,20
17,26
11,15,18
15,25
15
15
15
15,19
12,20
12,20
t
RCH
t
RRH
t
CLZ
t
OFF1
t
OFF2
t
WCS
t
WCH
t
WCR
t
WP
t
RWL
t
CWL
t
DS
t
DH
t
DHR
t
RWD
t
AWD
t
CWD
t
T
t
REF
t
REF
t
RPC
t
CSR
t
CHR
t
OEH
t
OES
t
OEHC
t
OEP
t
ORD
t
CLCH
t
COH
t
WHZ
t
RASS
t
RPS
t
CHS
CAS
to Output in Low-Z
Output Buffer Turn-off Delay From
CAS
or
RAS
Output Buffer Turn-off to
OE
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time(Reference to
RAS
)
Write Command Pulse Width
Write Command to
RAS
Lead Time
Write Command to
CAS
Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to
RAS
)
RAS
to
WE
Delay Time
Column Address to
WE
Delay Time
11
11
11,18
2,3
CAS
to
WE
Delay Time
Transition Time (rise or fall)
Refresh Period (512 cycles)
Refresh Period (512 cycles) Self Refresh
RAS
to
CAS
Precharge Time
CAS
Setup Time(CBR REFRESH)
CAS
Hold Time(CBR REFRESH)
OE
Hold Time From
WE
During Read-Mode-
Write Cycle
1,18
1,19
16
OE
Low to
CAS
High Setup Time
OE
High Hold Time From
CAS
High
OE
Precharge Time
OE
Setup Prior to
RAS
During Hidden Refresh
Cycle
Last
CAS
Going Low to First
CAS
Returning
High
Data Output Hold After
CAS
Returning Low
Output Disable Delay From
WE
Self Refresh
RAS
Low Pulse width
Self Refresh
RAS
High Precharge Time
Self Refresh
CAS
Hold Time
ns
ns
ns
21
µ
s
ns
ns
27,28
27,28
27,28
Elite Memory Technology Inc
Publication Date: Agu. 2001
Revision
:
1.3
5/16
