N02L163WN1AB-55I
| Model | N02L163WN1AB-55I |
| Description | 2Mb Ultra-Low Power Asynchronous CMOS SRAM |
| PDF file | Total 11 pages (File size: 264K) |
| Chip Manufacturer | ETC |
NanoAmp Solutions, Inc.
Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Output Load
Operating Temperature
N02L163WN1A
0.1V
CC
to 0.9 V
CC
5ns
0.5 V
CC
CL = 30pF
-40 to +85
o
C
Timing
Item
Read Cycle Time
Address Access Time
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
Address Setup Time
Write Recovery Time
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
Symbol
t
RC
t
AA
t
CO
t
OE
t
LB
, t
UB
t
LZ
t
OLZ
t
LBZ
, t
UBZ
t
HZ
t
OHZ
t
LBHZ
, t
UBHZ
t
OH
t
WC
t
CW
t
AW
t
LBW
, t
UBW
t
WP
t
AS
t
WR
t
WHZ
t
DW
t
DH
t
OW
40
0
10
10
5
10
0
0
0
10
70
50
50
50
40
0
0
20
35
0
10
20
20
20
2.3 - 3.6 V
Min.
70
70
70
35
35
10
5
10
0
0
0
10
55
40
40
40
40
0
0
20
20
20
20
Max.
2.7 - 3.6 V
Min.
55
55
55
30
30
Max.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(DOC# 14-02-014 REV L ECN# 01-1000)
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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