P01N02LMB
| Model | P01N02LMB |
| Description | N-Channel Logic Level Enhancement Mode Field Effect Transistor |
| PDF file | Total 3 pages (File size: 48K) |
| Chip Manufacturer | ETC |
NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P01N02LMB
SOT-23 (M3)
D
PRODUCT SUMMARY
V
(BR)DSS
25V
R
DS(ON)
180mΩ
I
D
1.2A
1. GATE
2. DRAIN
3. SOURCE
G
S
ABSOLUTE MAXIMUM RATINGS (T
C
= 25
°C
Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Power Dissipation
1
SYMBOL
V
GS
LIMITS
±15
1.2
1.0
12
0.6
0.5
-55 to 150
275
UNITS
V
T
C
= 25 °C
T
C
= 100 °C
I
D
I
DM
A
T
C
= 25 °C
T
C
= 100 °C
P
D
T
j
, T
stg
T
L
W
Operating Junction & Storage Temperature Range
Lead Temperature ( /
16
” from case for 10 sec.)
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
Junction-to-Case
Junction-to-Ambient
1
1
°C
SYMBOL
R
θJC
R
θJA
TYPICAL
MAXIMUM
65
230
UNITS
°C / W
Pulse width limited by maximum junction temperature.
ELECTRICAL CHARACTERISTICS (T
C
= 25 °C, Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
1
LIMITS
UNIT
MIN TYP MAX
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
I
D(ON)
1
V
GS
= 0V, I
D
= 250
µA
V
DS
= V
GS
, I
D
= 250
µA
V
DS
= 0V, V
GS
= ±15V
V
DS
= 20V, V
GS
= 0V
V
DS
= 20V, V
GS
= 0V, T
J
= 125 °C
V
DS
= 10V, V
GS
= 10V
V
GS
= 7V, I
D
= 1.2A
V
GS
= 10V, I
D
= 1.2A
V
DS
= 20V, I
D
= 1.2A
25
0.7
1.0
2.5
±250
25
250
1.2
220
180
16
250
220
V
nA
µA
A
mΩ
S
Drain-Source On-State Resistance
Forward Transconductance
1
R
DS(ON)
g
fs
1
AUG-18-2001
