P06P03LDG
| Model | P06P03LDG |
| Description | P-Channel Logic Level Enhancement Mode Field Effect Transistor |
| PDF file | Total 5 pages (File size: 275K) |
| Chip Manufacturer | ETC |
NIKO-SEM
P-Channel Logic Level Enhancement
Mode Field Effect Transistor
P06P03LDG
TO-252
Lead-Free
D
PRODUCT SUMMARY
V
(BR)DSS
-30
R
DS(ON)
45mΩ
I
D
-12A
G
S
1. GATE
2. DRAIN
3. SOURCE
ABSOLUTE MAXIMUM RATINGS (T
C
= 25
°C
Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Power Dissipation
1
SYMBOL
V
DS
V
GS
LIMITS
-30
±20
-12
-10
-30
48
20
-55 to 150
UNITS
V
V
T
C
= 25 °C
T
C
= 70 °C
I
D
I
DM
A
T
C
= 25 °C
T
C
= 70 °C
P
D
T
j
, T
stg
W
Operating Junction & Storage Temperature Range
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE
Junction-to-Case
Junction-to-Ambient
1
2
°C
UNITS
°C / W
°C / W
SYMBOL
R
θJ
c
R
θJA
TYPICAL
MAXIMUM
3
75
Pulse width limited by maximum junction temperature.
Duty cycle
≤
1%
ELECTRICAL CHARACTERISTICS (T
C
= 25
°C,
Unless Otherwise Noted)
PARAMETER
SYMBOL
TEST CONDITIONS
STATIC
Drain-Source Breakdown Voltage
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
1
Drain-Source On-State
Resistance
1
Forward Transconductance
1
V
(BR)DSS
V
GS(th)
I
GSS
I
DSS
I
D(ON)
R
DS(ON)
g
fs
V
GS
= 0V, I
D
= -250µA
V
DS
= V
GS
, I
D
= -250µA
V
DS
= 0V, V
GS
= ±20V
V
DS
= -24V, V
GS
= 0V
V
DS
= -20V, V
GS
= 0V, T
J
= 125 °C
V
DS
= -5V, V
GS
= -10V
V
GS
= -4.5V, I
D
=- 10A
V
GS
= -10V, I
D
= -12A
V
DS
= -10V, I
D
= -12A
-30
60
37
16
75
45
-30
-1
-1.5
-3.0
±250 nA
1
10
µA
A
mΩ
S
V
LIMITS
UNIT
MIN TYP MAX
AUG-17-2004
1
