PCS3I624Z05BG-08-ST
| Model | PCS3I624Z05BG-08-ST |
| Description | IC 100 MHz, OTHER CLOCK GENERATOR, PDSO8, 0.150 INCH, GREEN, SOIC-8, Clock Generator |
| PDF file | Total 15 pages (File size: 1M) |
| Chip Manufacturer | PULSECORE |
PCS3P624Z05B/C and PCS3P624Z09B/C
High Frequency Timing-Safe™
Peak EMI Reduction IC
General Features
•
High Frequency Clock distribution with Timing-Safe™
Peak EMI Reduction
•
Input frequency range: 50MHz - 100MHz
•
Multiple low skew Timing-safe™ Outputs:
PCS3P624Z05: 5 Outputs
PCS3P624Z09: 9 Outputs
•
External Input-Output Delay Control option
•
Supply Voltage: 3.3V±0.3V
•
Commercial and Industrial temperature range
•
Packaging Information:
ASM3P624Z05: 8 pin SOIC, and TSSOP
ASM3P624Z09:16 pin SOIC, and TSSOP
•
True Drop-in Solution for Zero Delay Buffer,
ASM5P2305A / 09A
with Peak EMI reduction. PCS3P624Z05 is an eight-pin
version, accepts one reference input and drives out five
low-skew Timing-Safe™ clocks. PCS3P624Z09 accepts
one reference input and drives out nine low-skew Timing-
Safe™clocks.
PCS3P624Z05/09 has a DLY_CTRL for adjusting the
Input-Output clock delay, depending upon the value of
capacitor connected at this pin to GND.
PCS3P624Z05/09 operates from a 3.3V supply and is
available in two different packages, as shown in the
ordering information table, over commercial and Industrial
temperature range.
Application
PCS3P624Z05/09 is targeted for use in Displays and
memory interface systems.
Functional Description
PCS3P624Z05/09 is a versatile, 3.3V Zero-delay buffer
designed to distribute high frequency Timing-Safe™ clocks
General Block Diagram
PLL
CLKIN
DLY_CTRL
CLKOUT1
CLKOUT2
CLKOUT3
PLL
MUX
DLY_CTRL
CLKOUTA1
CLKOUTA2
CLKOUTA3
CLKIN
PCS3P624Z05B/C
CLKOUTA4
CLKOUT4
S2
S1
Select Input
Decoding
CLKOUTB1
CLKOUTB2
CLKOUTB3
PCS3P624Z09B/C
CLKOUTB4
©2010 SCILLC. All rights reserved.
JANUARY 2010 – Rev1
Publication Order Number:
PCS3P624Z05/D
