S1028C1
| Model | S1028C1 |
| Description | High Speed Clock and Data Recovery for Fiber Optic Applications |
| PDF file | Total 25 pages (File size: 515K) |
| Chip Manufacturer | INFINEON |
FOA3251B1
S1028C1
Functional Description
2
Functional Description
The FOA3251 consists of a clock and data recovery block (CDR), a clock multiplier unit
(CMU) and a programmable delay line.
2.1
Pin Configuration
(top view)
36 35 34 33 32 31 30 29 28 27 26 25
LLOS
N2V5
37
38
39
40
41
42
43
44
45
46
47
48
1 2 3 4 5 6 7 8 9 10 11 12
P-LQFP-48-1
24
23
22
21
20
19
18
17
16
15
14
13
V
EE
V
CC alarm
LOL
LOS
RESET
XTAL IN
XTAL OUT
V
CC
V
CC
DELAY2
DELAY1
DELAY0
V
CC
DATA IN
V
CC
DATA IN
V
CC
V
F01
V
CC
PLL1 UP
PLL1 DN
TEST
V
CC
V
CC
V
CC
CLK TR
CLK TR
V
CC
DATA TR
DATA TR
V
CC
V
CC
V
EE
V
EE
TESTLOS
TESTCLK
V
CC
V
CC
V
CC
V
CC
V
CC
PLL2 DN
PLL2 UP
V
F02
V
CCLC
V
EELC
ITP11416
Figure 1
Pin Configuration
Data Sheet
6
V1.0, 1999-08
