U2391B
| Model | U2391B |
| Description | Quartz Controlled Pulse Generator |
| PDF file | Total 7 pages (File size: 72K) |
| Chip Manufacturer | TEMIC |
U2391B
Pin Description
Pin
1
2
3
4
5, 6
7
8
Symbol
Period
GND
Output
Contr.
Osc.
Test
V
S
Function
Period selection input
Ground
Output control pulse
Control input
Quartz-oscillator input
Test logic input/output
Supply voltage
Period
1
8
V
S
Test
Osc.
GND
Output
2
7
3
6
Contr.
4
5
Osc.
9611805
Figure 2. Pinning
Description
Pin 1, Period Selection Logic
Period selection at Pin 1 is as follows:
Pin 1 = open,
t = 36
s
Pin 1 = ground
t
= 1 s
Pin 1 = V
S
(Pin 8),
t
= 60 s
D
An interruption is ignored (Pin 4 =
put pulse time.
) during the out-
D
When Pin 4 is switched to V
S
during the output pulse
time
*
this output pulse will be reseated.
Pin 5, 6 Quartz-Oscillator Input
The propagated period time selection is based on circuit
with a low cost clock quartz of 32.768 kHz.
Pin 2, Ground
Pin 3, Output Stage
Output stage, being short circuit protected is limited to a
current value of typical 150 mA. Apart from it, there is a
voltage limitation which controls the power stage at the
rate of V
3
28.8 to 32 V and serves as an active Z-diode.
Output pulse width is 31.25 ms when quartz frequency is
32.768 kHz. It is independent of the selected period.
Pin 7, Test Logic, Figure 2, 3
To test the circuit in a reasonable time, it is possible to
control the divider (f
o
= 16 Hz) at Pin 7 as well as to feed
in a higher frequency to the programmed residual counter
(f
i
2 kHz
).
w
v
Pin 4, Control Logic
Pin 8, Supply Voltage
An operating voltage of 4.5 V is necessary for the func-
tioning of the circuit, although an internal switch-on
monitoring allows it to operate with a voltage of 3.6 V.
This means that there is sufficient reliability for the per-
formance of the circuit.
The circuit is designed for 12 V 10% with internal sup-
ply voltage limitation of typical 15 V. In case of higher
voltages there is a need of a series resistance and buffer
capacitance as shown in figure 1.
D
Counting delay is typ 1.5 s (maximum 8 s) when Pin 4
D
Programmable residual divider
t
D
Clock input to the
2
7
y
1 s is reseated if
Pin 4 is connected to Pin 8. This results in an absolute
tolerance, at the start across “Reset/End” to be
v
1 s.
divider is inhibited, if Pin 4 is
connected to the ground (Pin 2). Absolute tolerance
for every interruption is 0.488 ms.
is open and V
S
is switched on.
"
v
2 (7)
Preliminary Information
TELEFUNKEN Semiconductors
Rev. A1, 30-May-96
