U2790B-BFP
| Model | U2790B-BFP |
| Description | Modulator, Quadraphase, 0MHz Min, 250MHz Max, SO-16, 16 PIN |
| PDF file | Total 12 pages (File size: 183K) |
| Chip Manufacturer | TEMIC |
U2790B
Application Notes
Noise Floor and Settling Time
In order to reduce noise on the power-down control input
and improve the wide-off noise floor of the 900-MHz RF
output signal, capacitor C
PD
should be connected from
Pin 6 to ground in the shortest possible way.
The settling time has to be considered for the system un-
der design. For GSM applications, a value of C
PD
= 1 nF
defines a settling time, t
sPD
, equal or less than 3
m
s. This
capacitance does not have any influence on the noise floor
within the relevant GSM mask. For mobile applications
the mask requirements can be achieved very easily with-
out C
PD
.
A significant improvement of the wide-off noise floor is
obtainable with C
PD
greater than 100 nF. Such values are
recommended for applications where the settling time is
not critical such as in base stations. Coupling capacitors
for LO
i
and RF
O
also have a certain impact on the settling
time. The values used for the measurements are
C
LOi
= 100 pF and C
RFo
= 1 nF.
Baseband Coupling
U2790B-FP (SO16) has an integrated biasing network
which allows AC coupling of the baseband signal at a low
count of external components. The bias voltage is
2.5 V 0.15 V.
"
Figure 19 shows the baseband input circuitry with a resis-
tance of 3.2 k
W
for each asymmetric input. The internal
DC offset between A and A, and B and B is typically <
1 mV with a maximum of
3 mV. DC coupling is also
possible with an external DC voltage of 2.5 0.15 V.
"
"
"
Circuitries
Mixer input stage
3.2 k
W
A
,
B
A
,
B
94 7869 e
Figure 19. Baseband input circuitry
V
S
RF
O
20
W
3
LO
i
12
50
W
20 pF
94 8508
94 8509
Figure 20. RF output circuitry
Figure 21. L
O
input circuitry
10 (12)
Rev. A3, 20-May-99
