U62H1708TK55
| Model | U62H1708TK55 |
| Description | Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, TSOP1-32 |
| PDF file | Total 10 pages (File size: 175K) |
| Chip Manufacturer | SIMTEK |
U62H1708
Automotive Fast 128K x 8 SRAM
Features
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131072 x 8 bit static CMOS RAM
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35 and 55 ns Access Time
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Common data inputs and
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Description
The U62H1708 is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active.
During the active state (E1 = L and
E2 = H) each address change
leads to a new Read cycle. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (I
O
= 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E1
and E2, all inputs consist of NOR
gates, so that no pull-up/pull-down
resistors are required.
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data outputs
Three-state outputs
Typ. operating supply current
35 ns: 45mA
55 ns: 30mA
Standby current <200µA at 125°C
TTL/CMOS-compatible
Power supply voltage 5 V
Operating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity >100 mA
Package: SOP32 (450 mil)
TSOP I 32
sTSOP I 32
Pin Configuration
Pin Description
n.c.
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
VCC
A15
E2
W
A13
A8
A9
A11
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
A11
A9
A8
A13
W
E2
A15
VCC
n.c.
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
G
A10
E1
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
Signal Name Signal Description
A0 - A16
DQ0 - DQ7
E1
E2
G
W
VCC
VSS
n.c.
Address Inputs
Data In/Out
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
not connected
SOP
25
24
23
22
21
20
19
18
17
TSOP
25
sTSOP
24
23
22
21
20
19
18
17
Top View
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April 21, 2004
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