U62H256AS2A55LLG1
| Model | U62H256AS2A55LLG1 |
| Description | AUTOMOTIVE FAST 32K X 8 SRAM |
| PDF file | Total 10 pages (File size: 162K) |
| Chip Manufacturer | ETC |
U62H256A
Automotive Fast 32K x 8 SRAM
Features
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32768 x 8 bit static CMOS RAM
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35 and 55 ns Access Time
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Common data inputs and
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Description
go High-Z until the new information
is available. The data outputs have
no preferred state. The Read cycle
is finished by the falling edge of W,
or by the rising edge of E, respec-
tively.
Data retention is guaranteed down
to 2 V. With the exception of E, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required.
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The U62H256A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
data outputs
- Read
- Standby
Three-state outputs
- Write
- Data Retention
Typ. operating supply current
The memory array is based on a
35 ns: 45 mA
6-transistor cell.
55 ns: 30 mA
Standby current < 50 µA at 125 °C The circuit is activated by the fal-
ling edge of E. The address and
TTL/CMOS-compatible
control inputs open simultaneously.
Power supply voltage 5 V
According to the information of W
Operating temperature range
-40 °C to 85 °C
and G, the data inputs, or outputs,
-40 °C to 125 °C
are active. In a Read cycle, the
data outputs are activated by the
QS 9000 Quality Standard
falling edge of G, afterwards the
ESD protection > 2000 V
(MIL STD 883C M3015.7)
data word will be available at the
outputs DQ0-DQ7. After the
Latch-up immunity >100 mA
address change, the data outputs
Package: SOP28 (300/330 mil)
Pin Configuration
Pin Description
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A14
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
SOP
22
21
20
19
18
17
16
15
Top View
April 20, 2004
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