U630H04SC45
| Model | U630H04SC45 |
| Description | Non-Volatile SRAM, 512X8, 45ns, CMOS, PDSO28, 0.300 INCH, SOP-28 |
| PDF file | Total 14 pages (File size: 212K) |
| Chip Manufacturer | CYPRESS |
Preliminary
U630H04
HardStore
512 x 8 nvSRAM
Features
F
Packages:
Description
F
High-performance CMOS nonvo-
latile static RAM 512 x 8 bits
F
25 and 45 ns Access Times
F
12 and 25 ns Output Enable
Access Times
F
Unlimited Read and Write to
SRAM
F
Hardware STORE Initiation
(STORE Cycle Time < 10 ms)
F
Automatic STORE Timing
F
10 STORE cycles to EEPROM
F
10 years data retention in
EEPROM
F
Automatic RECALL on Power Up
F
Hardware RECALL Initiation
(RECALL Cycle Time < 20
µs)
F
Unlimited RECALL cycles from
EEPROM
F
Single 5 V
±
10 % Operation
F
Operating temperature ranges:
5
PDIP28 (300 mil)
PDIP28 (600 mil)
SOP28 (300 mil)
F
F
0 to 70
°C
-40 to 85
°C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
The U630H04 has two separate
modes of operation: SRAM mode
and nonvolatile mode, determined
by the state of the NE pin.
In SRAM mode, the memory ope-
rates as an ordinary static RAM. In
nonvolatile operation, data is trans-
ferred in parallel from SRAM to
EEPROM or from EEPROM to
SRAM. In this mode SRAM
functions are disabled.
The U630H04 is a fast static RAM
(25 and 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation), or from the
EEPROM to the SRAM (the
RECALL operation) are initiated
through the state of the NE pin.
The U630H04 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
NE
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Top View
PDIP
SOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
n.c.
A8
n.c.
n.c.
G
n.c.
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A8
DQ0 - DQ7
E
G
W
NE
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Nonvolatile Enable
Power Supply Voltage
Ground
December 12, 1997
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