U631H16BD1K35
| Model | U631H16BD1K35 |
| Description | SOFTSTORE 2K X 8 NVSRAM |
| PDF file | Total 12 pages (File size: 277K) |
| Chip Manufacturer | ETC |
U631H16
SoftStore
2K x 8 nvSRAM
Features
F
Packages:
F
High-performance CMOS non-
volatile static RAM 2048 x 8 bits
F
25, 35 and 45 ns Access Times
F
12, 20 and 25 ns Output Enable
Access Times
F
Software STORE Initiation
(STORE Cycle Time < 10 ms)
F
Automatic STORE Timing
F
10 STORE cycles to EEPROM
F
10 years data retention in
EEPROM
F
Automatic RECALL on Power Up
F
Software RECALL Initiation
(RECALL Cycle Time < 20
µs)
F
Unlimited RECALL cycles from
EEPROM
F
Unlimited Read and Write to
SRAM
F
Single 5 V
±
10 % Operation
F
Operating temperature ranges:
5
PDIP28 (300 mil)
PDIP28 (600 mil)
SOP28 (300 mil)
SOP24 (300 mil)
Description
The U631H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U631H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM.
F
F
F
0 to 70 °C
-40 to 85 °C
CECC 90000 Quality Standard
ESD characterization according
MIL STD 883C M3015.7-HBM
(classification see IC Code
Numbers)
Data transfers from the SRAM to
the EEPROM (the STORE opera-
tion), or from the EEPROM to the
SRAM (the RECALL ) operation)
are initiated through software
sequences.
The U631H16 combines the high
performance and ease of use of a
fast SRAM with nonvolatile data
integrity.
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or write
accesses intervene in the sequence
or the sequence will be aborted.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvolatile
information is transferred into the
SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
Pin Description
n.c.
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
28
27
26
VCC
W
n.c.
A8
A9
n.c.
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
25
4
24
5
23
6
PDIP
22
7
SOP
21
8
28
9
20
10
19
11
18
12
17
13
16
14
15
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
SOP
19
24
18
17
16
15
14
13
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCC
VSS
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Top View
Top View
1
December 12, 1997
