U632H16SC25
| Model | U632H16SC25 |
| Description | Non-Volatile SRAM, 2KX8, 25ns, CMOS, PDSO28, 0.300 INCH, SOP-28 |
| PDF file | Total 14 pages (File size: 229K) |
| Chip Manufacturer | SIMTEK |
U632H16
PowerStore
2K x 8 nvSRAM
Features
High-performance CMOS non-
volatile static RAM 2048 x 8 bits
25, 35 and 45 ns Access Times
12, 20 and 25 ns Output Enable
Access Times
I
CC
= 15 mA at 200 ns Cycle
Time
Automatic STORE to EEPROM
on Power Down using external
capacitor
Hardware or Software initiated
STORE
(STORE Cycle Time < 10 ms)
Automatic STORE Timing
10
6
STORE cycles to EEPROM
100 years data retention in
EEPROM
Automatic RECALL on Power Up
Software RECALL Initiation
(RECALL Cycle Time < 20
µs)
Unlimited RECALL cycles from
EEPROM
Single 5 V
±
10 % Operation
Operating temperature ranges:
0 to 70
°C
-40 to 85
°C
QS 9000 Quality Standard
ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
RoHS compliance and Pb- free
Packages: PDIP28 (300 mil)
SOP28 (300 mil)
Description
The U632H16 has two separate
modes of operation: SRAM mode
and nonvolatile mode. In SRAM
mode, the memory operates as an
ordinary static RAM. In nonvolatile
operation, data is transferred in
parallel from SRAM to EEPROM or
from EEPROM to SRAM. In this
mode SRAM functions are disab-
led.
The U632H16 is a fast static RAM
(25, 35, 45 ns), with a nonvolatile
electrically
erasable
PROM
(EEPROM) element incorporated
in each static memory cell. The
SRAM can be read and written an
unlimited number of times, while
independent nonvolatile data resi-
des in EEPROM. Data transfers
from the SRAM to the EEPROM
(the STORE operation) take place
automatically upon power down
using charge stored in an external
100 µF capacitor. Transfers from
the EEPROM to the SRAM (the
RECALL operation) take place
Pin Description
automatically on power up. The
U632H16 combines the high per-
formance and ease of use of a fast
SRAM with nonvolatile data inte-
grity.
STORE cycles also may be initia-
ted under user control via a soft-
ware sequence or via a single pin
(HSB).
Once a STORE cycle is initiated,
further input or output are disabled
until the cycle is completed.
Because a sequence of addresses
is used for STORE initiation, it is
important that no other read or
write accesses intervene in the
sequence or the sequence will be
aborted.
RECALL cycles may also be initia-
ted by a software sequence.
Internally, RECALL is a two step
procedure. First, the SRAM data is
cleared and second, the nonvola-
tile information is transferred into
the SRAM cells.
The RECALL operation in no way
alters the data in the EEPROM
cells. The nonvolatile data can be
recalled an unlimited number of
times.
Pin Configuration
VCAP
n.c.
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
VCCX
W
HSB
A8
A9
n.c.
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
Signal Name
A0 - A10
DQ0 - DQ7
E
G
W
VCCX
VSS
VCAP
HSB
Signal Description
Address Inputs
Data In/Out
Chip Enable
Output Enable
Write Enable
Power Supply Voltage
Ground
Capacitor
Hardware Controlled Store/Busy
PDIP
22
SOP
21
20
19
18
17
16
15
Top View
April 7, 2005
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