W130
| Model | W130 |
| Description | Spread Spectrum Desktop/Notebook System Clock |
| PDF file | Total 8 pages (File size: 120K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
W130
Spread Spectrum Desktop/Notebook System Clock
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Six copies of CPU Clock
• Eight copies of PCI Clock (synchronous w/CPU clock)
• Two copies of 14.318-MHz IOAPIC Clock
• Two copies of 48-MHz USB Clock
• Three buffered copies of 14.318-MHz reference input
• Input is a 14.318-MHz XTAL or reference signal
• Selectable 100-MHz or 66-MHz CPU Clocks
• Power management control input pins
• Test mode and output three-state capability
CPU0:5 Clock Skew: ...................................................175 ps
PCI_F, PCI1:7 Clock Skew: ......................................... 500 ps
CPU to PCI Clock Skew: .............. 1.5 to 4.0 ns (CPU Leads)
Logic inputs have 250-kΩ pull-up resistors except SEL100/66#.
Table 1. Pin Selectable Frequency
SEL
100/66#
0
0
0
0
1
1
Supply Voltages: ....................................... V
DDQ3
= 3.3V±5%
V
DDQ2
= 2.5V±5%
CPU Clock Jitter: ........................................................ 200 ps
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
HI-Z
66.6
66.6
66.6
X1/2
100
100
100
PCI
HI-Z
33.3
33.3
33.3
X1/6
33.3
33.3
33.3
SPREAD#=0
Don’t Care
±0.9% Center
–1% Down
–0.5% Down
Don’t Care
±0.9% Center
–1% Down
–0.5% Down
Key Specifications
Block Diagram
VDDQ3
REF0
X1
X2
XTAL
OSC
PLL Ref Freq
VDDQ2
APIC0
APIC1
VDDQ2
CPU_STOP#
Stop
Clock
Control
100/66#_SEL
SEL0
SEL1
SPREAD#
PLL 1
÷2/÷3
CPU0
CPU1
CPU2
CPU3
CPU4
CPU5
VDDQ3
PCI_F
Stop
Clock
Control
PCI_STOP#
VDDQ3
PCI4
PCI5
PCI6
PCI7
PWR_DWN#
Power
Power
Down
Down
Control
Control
VDDQ3
PLL2
48MHz
48MHz
PCI1
PCI2
PCI3
REF1
REF2
Pin Configuration
REF0
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
48MHz
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ3
REF2
VDDQ2
APIC0
APIC1
VDDQ2
CPU0
CPU1
CPU2
CPU3
GND
VDDQ2
CPU4
CPU5
GND
VDDQ3
GND
PCI_STOP#
CPU_STOP#
PWRDWN#
SPREAD#
SEL0
SEL1
SEL100/66#
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134 •
408-943-2600
October 27, 1999, rev. **
