W134SH
| Model | W134SH |
| Description | Direct Rambus Clock Generator |
| PDF file | Total 12 pages (File size: 200K) |
| Chip Manufacturer | CYPRESS |
W134M/W134S
Table 8. State Transition Latency Specifications
(continued)
Transition Latency
Transition
E
E
F
L
N
B,D
From
Clk Stop
Clk Stop
Normal
Test
Normal
To
Normal
Normal
Clk Stop
Normal
Test
Parameter
t
CLKON
t
CLKSETL
t
CLKOFF
t
CTL
t
CTL
Max.
10 ns
Description
Time from StopB until Clk/ClkB provides glitch-free
clock edges.
20 cycles Time from StopB to Clk/ClkB output settled to within 50
ps of the phase before CLK/CLKB was disabled.
5 ns
3 ms
3 ms
1 ms
Time from StopB to Clk/ClkB output disabled.
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding t
DISTLOCK
).
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding t
DISTLOCK
).
Time from PwrDnB to the device in Power-down.
Normal or Clk Stop Power-down t
POWERDN
Figure 5
shows that the Clk Stop to Normal transition goes
through three phases. During t
CLKON
, the clock output is not
specified and can have glitches. For t
CLKON
< t < t
CLKSETL
, the
clock output is enabled and must be glitch-free. For
t > t
CLKSETL
, the clock output phase must be settled to within
50 ps of the phase before the clock output was disabled. At
this time, the clock output must also meet the voltage and
timing specifications of
Table
. The outputs are in a
high-impedance state during the Clk Stop mode.
Table 9. Distributed Loop Lock Time Specification
Parameter
t
DISTLOCK
Description
Time from when Clk/ClkB output is settled to when the phase error between SynclkN and
PclkM falls within the t
ERR,PD
spec in
Table
.
Min.
Max.
5
Unit
ms
Table 10.Supply and Reference Current Specification
Parameter
I
POWERDOWN
I
CLKSTOP
I
NORMAL
I
REF,PWDN
I
REF,NORM
Description
“Supply” current in Power-down state (PwrDnB 1 = 0)
“Supply” current in Clk Stop state (StopB = 0)
“Supply” current in Normal state (StopB = 1,PwrDnB = 1)
Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)
Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1)
Min.
–
–
–
–
–
Max.
250
65
100
50
2
Unit
µA
mA
mA
µA
mA
Document #: 38-07426 Rev. *B
Page 7 of 12
