W147G
| Model | W147G |
| Description | Frequency Generator for Integrated Core Logic |
| PDF file | Total 12 pages (File size: 143K) |
| Chip Manufacturer | CYPRESS |
PRELIMINARY
AC Electrical Characteristics
T
A
= 0°C to +70°C, V
DDQ3
= 3.3V±5%, V
DDQ2
= 2.5V±5%
f
XTL
= 14.31818 MHz
Spread Spectrum function turned off
W147G
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
[16]
66.6-MHz Host
Parameter
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
T
Period
T
HIGH
T
LOW
T
RISE
T
FALL
tp
ZL
, tp
ZH
tp
LZ
, tp
ZH
t
stable
Description
Host/CPUCLK Period
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
SDRAM CLK Period
SDRAM CLK High Time
SDRAM CLK Low Time
SDRAM CLK Rise Time
SDRAM CLK Fall Time
APIC CLK Period
APIC CLK High Time
APIC CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
3V66 CLK Period
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
PCI CLK Period
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
Output Enable Delay (All outputs)
Output Disable Delay (All outputs)
All Clock Stabilization from Power-Up
Min.
15.0
5.2
5.0
0.4
0.4
10.0
3.0
2.8
0.4
0.4
60.0
25.5
25.3
0.4
0.4
15.0
5.25
5.05
0.5
0.5
30.0
12.0
12.0
0.5
0.5
1.0
1.0
Max.
15.5
N/A
N/A
1.6
1.6
10.5
N/A
N/A
1.6
1.6
64.0
N/A
N/A
1.6
1.6
16.0
N/A
N/A
2.0
2.0
N/A
N/A
N/A
2.0
2.0
10.0
10.0
3
100-MHz Host
Min.
10.0
3.0
2.8
0.4
0.4
10.0
3.0
2.8
0.4
0.4
60.0
25.5
25.3
0.4
0.4
15.0
5.25
5.05
0.5
0.5
30.0
12.0
12.0
0.5
0.5
1.0
1.0
Max.
10.5
N/A
N/A
1.6
1.6
10.5
N/A
N/A
1.6
1.6
64.0
N/A
N/A
1.6
1.6
16.0
N/A
N/A
2.0
2.0
N/A
N/A
N/A
2.0
2.0
10.0
10.0
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
16, 17
19
20
16, 18
19
20
16
19
20
16
19
20
Notes
16
19
20
Notes:
16. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
17. T
HIGH
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
18. T
LOW
is measured at 0.4V for all outputs.
19. The time specified is measured from when V
DDQ3
achieves its nominal operating level (typical condition V
DDQ3
= 3.3V) until the frequency output is stable and
operating within specification.
20. T
RISE
and T
FALL
are measured as a transition through the threshold region V
ol
= 0.4V and V
oh
= 2.0V (1 mA) JEDEC specification.
10
