W152-3GT
| Model | W152-3GT |
| Description | PLL Based Clock Driver, 8 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, SOIC-16 |
| PDF file | Total 8 pages (File size: 146K) |
| Chip Manufacturer | CYPRESS |
W152
1
2
3
Ref In
QA0
QA1
Power
FB In
QA3
QA2
Power
Ground
QB3
QB2
SEL0
16
15
14
13
12
11
10
9
See Note 3
VDD
0.1
µF
10
µF
Ferrite
Bead
3.3V
Supply
VDD
0.1
µF
4
5
Ground
6
7
VDD or GND (for desired operation mode)
8
QB0
QB1
SEL1
VDD or GND (for desired operation mo
Figure 1. Schematic
[4]
Note:
3. Pin 16 needs to be connected to one of the outputs from either bank A or bank B, it should not be connected to both. Pins 2 and 10 are shown here as
examples. None of the outputs should be considered as preferred for the feedback path.
How to Implement Zero Delay
Typically, zero delay buffers (ZDBs) are used because a de-
signer wants to provide multiple copies of a clock signal in
phase with each other. The whole concept behind ZDBs is that
the signals at the destination chips are all going HIGH at the
same time as the input to the ZDB. In order to achieve this,
layout must compensate for trace length between the ZDB and
the target devices. The method of compensation is described
below.
External feedback is the trait that allows for this compensation.
The PLL on the ZDB will cause the feedback signal to be in
phase with the reference signal. When laying out the board,
match the trace lengths between the output being used for
feedback and the FBIN input to the PLL.
If it is desirable to either add a little delay, or slightly precede
the input signal, this may also be affected by either making the
trace to the FBIN pin a little shorter or a little longer than the
traces to the devices being clocked.
some other device. This implementation can be applied to any
device (ASIC, multiple output clock buffer/driver, etc.) which is
put into the feedback path.
Referring to
Figure 2,
if the traces between the ASIC/buffer
and the destination of the clock signal(s) (A) are equal in length
to the trace between the buffer and the FBIN pin, the signals
at the destination(s) device will be driven HIGH at the same
time the Reference clock provided to the ZDB goes HIGH.
Synchronizing the other outputs of the ZDB to the outputs form
the ASIC/Buffer is more complex however, as any propagation
delay in the ASIC/Buffer must be accounted for.
Reference
Signal
Feedback
Input
Zero
Delay
Buffer
ASIC/
Buffer
A
Inserting Other Devices in Feedback Path
Another nice feature available due to the external feedback is
the ability to synchronize signals up to the signal coming from
Figure 2. 6 Output Buffer in the Feedback Path
Document #: 38-07148 Rev. *A
Page 3 of 8
